• Title, Summary, Keyword: CDR

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Design of Optical Receiver with CDR using Delayed Data Topology (데이터 지연방식의 CDR을 이용한 광 송신기 설계)

  • Kim, Kyung-Min;Kang, Hyung-Won;Choi, Young-Wan
    • 한국정보통신설비학회:학술대회논문집
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    • pp.154-158
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    • 2005
  • In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.

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Properties of Alkali Hydrolyzed Polyester Fabric by CDR/Liquor-Flow Type (연속/액류방식에 의한 폴리에스테르 직물의 감량특성)

  • Seo, Mal-Yong;Park, Han-Do;Park, Ki-Su;Han, Sun-Ju
    • Textile Coloration and Finishing
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    • v.9 no.4
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    • pp.39-46
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    • 1997
  • In this study, Two types of polyester fabrics were hydrolysed with NaOH using the CDR m/c of pad-steam type and the Sofleena m/c of liquor-flow type to determine the alkali hydrolysis properties of polyester fabrics. The results were as follows: Under the same conditions, the weight loss of charmeuse was about 0.5% and 2~3% higher than that of pebble with CDR m/c and with Sofleena m/c, respectively. The weft density of pebble decreased about 14picks/inch with CDR m/c and 3picks/inch with Sofleena m/c comparing to the untreated sample at 18% of weight loss, while the weft density of charmeuse decreased about 5picks/inch with CDR m/c and 2picks/inch with Sofleena m/c at 20% of weight toss. K/S value decreased almost identically within about 11% weight loss of pebble and 8% of charmeuse processed with both CDR and Sofleena. However, in the above these weight losses, K/S value of the fabrics processed with Sofleena was higher than that of fabrics processed with CDR. The bending rigidity of warp direction of the fabrics ($2{\times}10^{-2}gf.cm^2 /cm$ higher for charmeuse and ($7{\times}10^{-3}gf.cm^2 /cm$ higher for pebble) processed with CDR m/c was higher than that of the fabrics processed with Sofleena m/c.

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Design of low jitter CDR using a single edge binary phase detector (단일 에지 이진위상검출기를 사용한 저 지터 클록 데이터 복원 회로 설계)

  • An, Taek-Joon;Kong, In-Seok;Im, Sang-Soon;Kang, Jin-Ku
    • Journal of IKEEE
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    • v.17 no.4
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    • pp.544-549
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    • 2013
  • This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.

The Influence of Physical Therapy on the Changes in Clinical Dementia Rating Scale in Long-stay Elderly Patients

  • Kim, Ji Sung
    • Journal of International Academy of Physical Therapy Research
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    • v.5 no.1
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    • pp.696-700
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    • 2014
  • This study was carried out to identify the influence of continuous physical therapy on long-stay elderly patients. This study classified 92 patients who had been hospitalized for one year into experimental group who continued to perform physical therapy and control group who did not conduct physical therapy and these two groups were classified into 0.5 point-questionable group, 1 point-mild dementia group, and 2 point-moderate dementia group based on the Clinical Dementia Rating Scale(CDR) when they were hospitalized in order to analyze the changes at the early stage of hospitalization and after one year has passed. As a result, it was appeared that both in CDR 0.5-point subgroup of questionable group and in CDR 1-point subgroup of mild dementia group, CDR was statistically significantly reduced in the experimental group whose physical therapy was continuously performed than in the control group whose physical therapy was not performed(p<.05) and that there was no significant difference in changes in the CDR between experimental group and control group in CDR 2-point group, which is a moderate dementia group.

Design of a 0.18$\mu$m CMOS 10Gbps CDR With a Quarter-Rate Bang-Bang Phase Detector (Quarter-Rate Bang-Bang 위상검출기를 사용한 0.18$\mu$m CMOS 10Gbps CDR 회로 설계)

  • Cha, Chung-Hyeon;Ko, Seung-O;Seo, Hee-Taek;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.13 no.2
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    • pp.118-125
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    • 2009
  • With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

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Design of Clock and Data Recovery Circuit for 622Mbps Optical Network (622Mbps급 광 통신망용 버스트모드 클럭/데이터 복원회로 설계)

  • Moon, Sung-Young;Lee, Sung-Chul;Moon, Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.2
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    • pp.57-63
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    • 2009
  • In this Paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of $2^7-1$, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

Correlation Analysis Between O/D Trips and Call Detail Record: A Case Study of Daegu Metropolitan Area (모바일 통신 자료와 O/D 통행량의 상관성 분석 - 대구광역시 사례를 중심으로)

  • Kim, Keun-uk;Chung, Younshik
    • Journal of The Korean Society of Civil Engineers
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    • v.39 no.5
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    • pp.605-612
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    • 2019
  • Traditionally, travel demand forecasts have been conducted based on the data collected by a survey of individual travel behavior, and their limitations such as the accuracy of travel demand forecasts have been also raised. In recent, advancements in information and communication technologies are enabling new datasets in travel demand forecasting research. Such datasets include data from global positioning system (GPS) devices, data from mobile phone signalling, and data from call detail record (CDR), and they are used for reducing the errors in travel demand forecasts. Based on these background, the objective of this study is to assess the feasibility of CDR as a base data for travel demand forecasts. To perform this objective, CDR data collected for Daegu Metropolitan area for four days in April including weekdays and weekend days, 2017, were used. Based on these data, we analyzed the correlation between CDR and travel demand by travel survey data. The result showed that there exists the correlation and the correlation tends to be higher in discretionary trips such as non-home based business, non-home based shopping, and non-home based other trips.

A CDR using 1/4-rate Clock based on Dual-Interpolator (1/4-rate 클록을 이용한 이중 보간 방식 기반의 CDR)

  • Ahn, Hee-Sun;Park, Won-Ki;Lee, Sung-Chul;Jeong, Hang-Geun
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.1
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    • pp.68-75
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    • 2009
  • In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

Comparison of Domestic and Foreign Design Standards for Overall Stability of Soil Nailed Slopes (쏘일네일 보강 비탈면의 전체 안정성에 대한 국내외 설계기준 비교)

  • Kim, Tae-Won;You, Kwang-Ho
    • Journal of the Korean Geoenvironmental Society
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    • v.20 no.6
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    • pp.5-13
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    • 2019
  • The international trend in soil nailed wall design has been evolved from the allowable stress design to limit state design and it is still currently ongoing. The design guidelines in Korea and Hong Kong still adopts the allowable stress design philosophy while those in others mostly do the limit state design. In this study, four soil nail design methods presented in the major design guidelines (U.S. FHWA GEC 7 (2015), Clouterre in France (1991), Soil nailing - best practice guidance in U.K. (CIRIA, 2005), Geoguide 7 in Hong Kong (2008) and Design standard for slope reinforcement work in Korea (KDS 11 70 15 f: 2016)) are described and analyzed in brief. The factor of safety and CDR (Capacity-to-Demand Ratio) which is used to measure the degree of conservatism of a design guide are obtained for the two cases. One is the design example presented in CIRIA (2005) and the other is in-situ loading test performed on the top of backfill of the soil nail wall to investigate the conservatism of design guidelines. It is revealed that the design method in overall stability of soil nail walls in domestic design method (CDR=0.78) is the most conservative and those by Clouterre (CDR=0.99, 1.09), Geoguide 7 (CDR=1.13, 0.97), U.S. FHWA (CDR=1.09, 1.07) and CIRIA (CDR=1.40, 1.16) in order from the second most conservative to the least conservative for the design example presented in CIRIA. For the in-situ loading test performed on the top of backfill of the soil nail wall, the order of conservatism is identical except that the places of Geoguide 7 (CDR=0.66, 0.72) and FHWA (CDR=0.73, 0.72) are changed. However, the results obtained among U.S. FHWA (2015) and Clouterre (1991) and Geoguide 7 (2008) are not so different.

A novel 622Mbps burst mode CDR circuit using two-loop switching

  • Han, Pyung-Su;Lee, Cheon-Oh;Park, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.4
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    • pp.188-193
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    • 2003
  • This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.