• Title, Summary, Keyword: Backplane

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A Design of Transmission Channel for 40Gb/s backplane Ethernet based on IEEE P802.3ba (IEEE P802.3ba 기반의 40 Gb/s 백플레인 이더넷 전송채널의 설계)

  • Yang, Choong-Reol;Kim, Kwang-Joon;Kim, Whan-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.4B
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    • pp.637-646
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    • 2010
  • For 40 Gb/s data transmission through electrical backplane trace up to 40 inch length on four layer fire-resistant (FR-4), we have designed the 40 Gb/s backplane channel model consisting of four channel 10 Gb/s. Simulation results show an enhancement of backplane channel characteristics excellent more than requirements specified in IEEE P802.3ba at 10 Gb/s. This paper provides a review of the structures and algorithms used in receive and adaptive equalization for 40 Gb/s backplane Ethernet. The use of this backplane channel model could achieves better receive equalizer at great data rate than 10 Gb/s.

Printed flexible OTFT backplane for electrophoretic displays

  • Ryu, Gi-Seong;Lee, Myung-Won;Song, Chung-Kun
    • Journal of Information Display
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    • v.12 no.4
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    • pp.213-217
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    • 2011
  • Printing technologies were applied to fabricate a flexible organic thin-film transistor (OTFT) backplane for electrophoretic displays (EPDs). Various printing processes were adopted to maximize the figures of each layer of OTFT: screen printing combined with reverse offset printing for the gate electrodes and scan bus lines with Ag ink, inkjet for the source/drain electrodes with glycerol-doped Poly (3,4-ethylenedioxythiophene): Poly (styrenesulfonate) (PEDOT:PSS), inkjet for the semiconductor layer with Triisopropylsilylethynyl (TIPS)-pentacene, and screen printing for the pixel electrodes with Ag paste. A mobility of $0.44cm^2/V$ s was obtained, with an average standard deviation of 20%, from the 36 OTFTs taken from different backplane locations, which indicates high uniformity. An EPD laminated on an OTFT backplane with $190{\times}152$ pixels on an 8-in panel was successfully operated by displaying some patterns.

A Design of the DFE based Receiver Equalizer for 40 Gb/s Backplane Ethernet (40Gb/s 백플레인 이더넷을 위한 DFE 수신등화기)

  • Yang, Choong-Reol;Kim, Kwang-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.2B
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    • pp.197-209
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    • 2010
  • In this paper, We have designed and analyzed a characteristics of backplane channel having 40 inch strip line length of four lanes and Flame Retardant four (PR-4) material, and have designed 40 Gb/s Receive and adaptive equalizer and its high-speed equalization algorithm using the backplane channel characteristics. For 40 Gb/s high-speed data communications pass through the backplane, a 10Gb/s 4 channel receive & equalizer with DFE except for FFE was proposed. This receive and equalizer meets the requirements of the IEEE Std P802.3ba standard-based receive equalizer to implement equalizers on the receive end of a 46 inch length's backplane channel.

Characteristics of Insertion Loss of Transmission Line with Equal Line Length Due to a Rectangular Aperture Size in a Backplane (백플레인 개구의 크기 변화에 따른 대칭 전송선로의 삽입 손실)

  • Jung, Sung-Woo;Cho, Jun-Ho;Kim, Ki-Chai
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.12
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    • pp.2518-2524
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    • 2009
  • This paper presents the backplane effects due to a rectangular aperture size for two-wire transmission line with equal line length crossing the changeable rectangular aperture in an infinite ground backplane. It is used to determine the characteristics of the backplane insertion loss of the transmission line from the load section in accordance with the backplane aperture size. The results show that the insertion gain and insertion loss are obtained for the specific frequency range when the transmission line is closed to the backplane aperture size. The insertion loss is decreased that the aperture horizontal length and vertical length is more than a=50 mm and b=20 mm. The measurements of insertion loss are performed to verify the theoretical analysis.

A Design Methodology on Signal Paths for Enhanced Signal Integrity of High-speed Communication System and a BIST Design for Backplane Boards Testing (고속 통신 시스템의 신호충실성 향상을 위한 선로 설계 방법론 및 Backplane Boards Testing를 위한 BIST 설계)

  • Jang, Jong-Gwon
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.4
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    • pp.1263-1270
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    • 2000
  • The operation frequency of High-speed Communication System becomes very fast with the advanced technology of VLSI chips and system implementation. There may exist various types of noise sources degrading the signal integrity in this system. The present main system is made of backplane, so faults can be brought whenever a board is removed, replaced or added. This backplane boards testing is a very important process to verify the operation of system. firstly, we model the effects of the internal noises in the High-speed Communication System to the signal line and propose a new design method to minimize these effects. For the design methodology, we derive the characterization value for each mode land them construct the optimal simulation model. We compare the result of own proposing method with that fo the existing methods, through simulation and show that the quality of High-speed Communication System is significantly enhanced. Secondary our proposing BIST for the Backplane Boards Testing is designed to guarantee that there is no fault in the high-speed communication system.

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Characteristics of Insertion Loss of Transmission Line with Different Line Length Crossing a Rectangular Aperture in a Backplane (백 플레인의 개구를 통과하는 길이가 다른 전송 선로의 삽입 손실 특성)

  • Jung, Sung-Woo;Kim, Ki-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.2
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    • pp.237-243
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    • 2008
  • This paper presents the backplane effects for two-wire transmission line with different line length crossing the rectangular aperture in an infinite ground backplane. The FDTD method is used to determine the characteristics of the backplane insertion loss and return loss of the transmission line in accordance with the transmission line spacing and additional wire lengths. The results show that the insertion gain is obtained for the narrow spacing of the transmission line and the insertion loss is appeared for the transmission line with the additional wire The measurements of return loss are performed to verify the theoretical analysis.

High Speed Serial Communication SRIO Backplane Implementation for TMS320C6678 (TMS320C6678기반의 고속 직렬통신용 SRIO backplane 구현)

  • Oh, Woojin;Kim, Yangsoo;Kang, Minsoo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.683-684
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    • 2016
  • The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.

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Simulation of Backplane Processor Bus and Extended Bus (Backplane Processor Bus 및 확장 Bus 시뮬레이션)

  • 김석환;김윤호;허창우
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.363-365
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    • 2003
  • 본 문서는 백프레인(backplane)에서 프로세서 버스(bus)의 데이터 전송 및 수신 특성을 알아보기 위해 HSPICE를 사용하여 시뮬레이션 하였다. 백프레인은 FR-4를 사용하였으며 버스 배선 길이와 스터브(stub) 길이에 대해 데이터 전송속도 특성을 시뮬레이션 하였다. 그리고, 구현 가능한 데이터 전송 및 수신 한계 속도에 대해 검토하였다. 시험결과는 백프레인에서 버스 한계속도에 영향을 주는 것이 버스에 연결된 스터브 길이와 수가 중요한 역할을 함을 알 수 있었다.

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Electrophoretic Display employing OTFT-Backplane on plastic substrate

  • Ryu, Gi-Seong;Lee, Myung-Won;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • pp.1178-1181
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    • 2006
  • We fabricated a flexible OTFT(organic thin film transistor) backplane for the electrophoretic display. The backplane was composed of $128{\times}96pixels$ on the Polyethylene Naphthalate substrate in which each pixel had one OTFT. The OTFTs employed bottom contact structure and used the cross-linked polyvinylphenol for gate insulator and pentacene for active layer

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Flexible OTFT-Backplane for Active Matrix Electrophoretic Display Panel

  • Lee, Myung-Won;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • pp.159-161
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    • 2007
  • We fabricated flexible OTFT-backplanes for the electrophoretic display(EPD). The OTFTs employed bottom contact structure on PEN substrate and used the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. Especially, we used PVA/Acryl double layers for passivation of backplane as well as for pixel dielectric layer between backplane and EPD panel. The OTFT-EPD panel worked successfully anddemonstrated to display some patterns.

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