• Title, Summary, Keyword: Asynchronous

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Implementation Of Asymmetric Communication For Asynchronous Iteration By the MPMD Method On Distributed Memory Systems (분산 메모리 시스템에서의 MPMD 방식의 비동기 반복 알고리즘을 위한 비대칭 전송의 구현)

  • Park Pil-Seong
    • Journal of Internet Computing and Services
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    • v.4 no.5
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    • pp.51-60
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    • 2003
  • Asynchronous iteration is a way to reduce performance degradation of some parallel algorithms due to load imbalance or transmission delay between computing nodes, which requires asymmetric communication between the nodes of different speeds. To implement such asynchronous communication on distributed memory systems, we suggest an MPMD method that creates an additional separate server process on each computing node, and compare it with an SPMD method that creates a single process per node.

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High -Level Synthesis for Asynchronous Systems using Transformational Approaches (변형기법을 이용한 비동기 시스템의 상위수준 합성기법)

  • 유동훈;이동익
    • Proceedings of the IEEK Conference
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    • pp.105-108
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    • 2002
  • Although asynchronous designs have become a promising way to develop complex modern digital systems, there is a few complete design framework for VLSI designers who wish to use automatic CAD tools. Especially, high-level synthesis is not widely concerned until now. In this paper we Proposed a method for high-level synthesis of asynchronous systems as a part of an asynchronous design framework. Our method performs scheduling, allocation, and binding, which are three subtasks of high-level synthesis, in simultaneous using a transformational approach. To deal with complexity of high-level synthesis we use neighborhood search algorithm such as Tabu search.

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Flexible Partitioning of CDFGs for Compact Asynchronous Controllers

  • Sretasereekul, Nattha;Okuyama, Yuichi;Saito, Hiroshi;Imai, Masashi;Kuroda, Kenichi;Nanya, Takashi
    • Proceedings of the IEEK Conference
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    • pp.1724-1727
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    • 2002
  • Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

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Low Power Reliable Asynchronous Digital Circuit Design for Sensor System (센서 시스템을 위한 저전력 고신뢰의 비동기 디지털 회로 설계)

  • Ahn, Jihyuk;Kim, Kyung Ki
    • Journal of Sensor Science and Technology
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    • v.26 no.3
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    • pp.209-213
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    • 2017
  • The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

An Algorithm for the Asynchronous PRT Vehicle Control System (비동기식 PRT 차량의 주행제어 알고리즘)

  • Chung, Sang-Gi;Jeong, Rag-Kyo;Kim, Baek-Hyun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.1
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    • pp.93-99
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    • 2011
  • A PRT vehicle's control method is presented in this paper. In the asynchronous vehicle control system, vehicles follow their leading vehicles. Leading vehicles are defined differently among the different types of track. The main topic of this paper is to present a method to define the leading vehicle among different types of track and the calculation algorithm of the safety length the following vehicle must maintain. Simulation program is developed using the algorithm and the results of the test run are presented. An asynchronous PRT vehicle control algorithm was presented by Szillat in the paper "A low level PRT Microsimulation, Dissertation, University of Bristol, 2001". But it is different from the algorithm in this paper. In the algorithm proposed by Markus, vehicles in the merging track are controlled synchronously, and its safety distance between the leading and the following car is evaluated after the establishment of the complicated future time-location table instead of simple equations proposed in this paper.

State Feedback Control of Asynchronous Sequential Machines with Uncontrollable Inputs: Application to Error Counters (제어 불능 입력이 존재하는 비동기 순차 머신의 상태 피드백 제어 및 오류 카운터로의 응용)

  • Yang, Jung-Min;Kwak, Seong-Woo
    • Journal of Institute of Control, Robotics and Systems
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    • v.15 no.10
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    • pp.967-973
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    • 2009
  • The model matching problem of asynchronous sequential machines is to design a corrective controller such that the stable-state behavior of the closed-loop system matches that of a prescribed model. In this paper, we address model matching when the external input set consists of controllable inputs and uncontrollable ones. Like in the frame of supervisory control of Discrete-Event Systems (DES), uncontrollable inputs cannot be disabled and must be transmitted to the plant without any change. We postulate necessary and sufficient conditions for the existence of a corrective controller that solves model matching despite the influence of uncontrollable events. Whenever a controller exists, the algorithm for its design is outlined. To illustrate the physical meaning of the proposed problem, the closed-loop system of an asynchronous machine with the proposed control scheme is implemented in VHDL code.

A Low Power Asynchronous MSP430 Processor for Ubiquitous Sensor Network (편재형 센서네트워크 노드를 위한 저전력 비동기 MSP430 프로세서)

  • Shin, Chi-Hoon;Shang, Belong;Oh, Myeong-Hoon;Kim, Young-Woo;Kim, Sung-Nam;Yakovlev, Alex;Kim, Sung-Woon
    • Proceedings of the KIEE Conference
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    • pp.451-453
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    • 2007
  • This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor. Both versions are then compared with existing commercial processors in terms of power consumption.

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Corrective Control of Asynchronous Sequential Machines with Input Disturbance II : Controller Design (입력 외란이 존재하는 비동기 순차 머신의 교정 제어 II : 제어기 설계)

  • Yang, Jung-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.9
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    • pp.1665-1675
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    • 2007
  • This paper presents the problem of controlling asynchronous sequential machines in the presence of input disturbances, which may be also regarded as an adversary in a game theoretic setting. The main objective is to provide necessary and sufficient condition for the existence of a corrective controller that solves model matching problem of an asynchronous machine suffering from input disturbance. The existence condition can be stated in terms of a simple comparison of two skeleton matrices. The proposed controller eliminates the adversarial effect of input disturbance and makes the controlled machine mimic the behavior of a model in stable-state way. Whenever controller exists, algorithms for their design are outlined and demonstrated in a case study.

A Novel Solid State Controller for Parallel Operated Isolated Asynchronous Generators in Pico Hydro Systems

  • Singh, Bhim;Kasal, Gaurav Kumar
    • Journal of Electrical Engineering and Technology
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    • v.2 no.3
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    • pp.358-365
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    • 2007
  • This paper deals with a novel solid state controller (NSSC) for parallel operated isolated asynchronous generators (IAG) feeding 3-phase 4-wire loads in constant power applications, such as uncontrolled pico hydro turbines. AC capacitor banks are used to meet the reactive power requirement of asynchronous generators. The proposed NSSC is realized using a set of IGBTs (Insulated gate bipolar junction transistors) based current controlled 4-leg voltage source converter (CC-VSC) and a DC chopper at its DC bus, which keeps the generated voltage and frequency constant in spite of changes in consumer loads. The complete system is modeled in MATLAB along with simulink and PSB (power system block set) toolboxes. The simulated results are presented to demonstrate the capability of isolated generating system consisting of NSSC and parallel operated asynchronous generators driven by uncontrolled pico hydro turbines and feeding 3-phase 4-wire loads.

Robust State Feedback Control of Asynchronous Sequential Machines and Its Implementation on VHDL (비동기 순차 머신의 강인한 상태 피드백 제어 및 VHDL 구현)

  • Yang, Jung-Min;Kwak, Seong-Woo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.12
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    • pp.2484-2491
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    • 2009
  • This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.