• Title, Summary, Keyword: Asynchronous

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Comparison of Starting Current Characteristics for Three-Phase Induction Motor Due to Phase-control Soft Starter and Asynchronous PWM AC Chopper

  • Thanyaphirak, Veera;Kinnares, Vijit;Kunakorn, Anantawat
    • Journal of Electrical Engineering and Technology
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    • v.12 no.3
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    • pp.1090-1100
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    • 2017
  • This paper presents the comparison of starting current characteristics of a three-phase induction motor fed by two types of soft starters. The first soft starter under investigation is a conventional AC voltage controller on the basis of a phase-control technique. The other is the proposed asynchronous PWM AC chopper which is developed from the conventional synchronous PWM AC chopper. In this paper, the proposed asynchronous PWM AC chopper control scheme is developed by generating only two asynchronous PWM signals for a three-phase main power circuit (6 switching devices) from a single voltage control signal which is compared with a single sawtooth carrier signal. By this approach, the PWM signals are independent and easy to implement since the PWM signals do not need to be synchronized with a three-phase voltage source. Details of both soft starters are discussed. The experimental and simulation results of the starting currents are shown. It is found that the asynchronous PWM AC chopper efficiently works as a suitable soft starter for the three-phase induction motor due to that the starting currents are reduced and are sinusoidal with less harmonic contents, when being compared with the starting current waveforms using the conventional phase-control starting technique. Also the proposed soft starter offers low starting electromagnetic torque pulsation.

Robust Control of Input/state Asynchronous Machines with Uncertain State Transitions (불확실한 상태 천이를 가진 입력/상태 비동기 머신을 위한 견실 제어)

  • Yang, Jung-Min
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.4
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    • pp.39-48
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    • 2009
  • Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

Design of an Asynchronous FIFO for SoC Designs Using a Valid Bit Scheme (SoC 설계를 위한 유효 비트 방식의 비동기 FIFO설계)

  • Lee Yong-hwan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.8
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    • pp.1735-1740
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    • 2005
  • SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

Corrective Control of Asynchronous Sequential Machines for Nondeterministic Model I: Reachability Analysis (비결정 모델에 대한 비동기 순차 회로의 교정 제어 I: 도달가능성 분석)

  • Yang, Jung-Min
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.45 no.4
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    • pp.1-10
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    • 2008
  • The problem of controlling asynchronous sequential machines is addressed in this paper. Corrective control means to make behavior of an asynchronous sequential machine equal to that of a given model. The main objective is to develope a corrective controller, especially when a model is given as nondeterministic, or a set of reference models. The structure of corrective control system for asynchronous sequential machines is addressed first, followed by description of nondeterministic models. Then, we propose a method for analyzing reachability of asynchronous machines and nondeterministic models. Proposed methods are demonstrated in an example.

Design of Receiver-Initiated Asynchronous MAC Protocol for Energy-Efficiency in WSNs (전력 효율을 위한 수신자 기반 비동기 센서 MAC 프로토콜 설계)

  • Park, In-Hye;Lee, Hyung-Keun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39B no.12
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    • pp.873-875
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    • 2014
  • In this paper we describe an asynchronous MAC protocol with receiver-initiated duty cycling for energy-efficiency in wireless sensor networks(WSN). Legacy asynchronous MAC protocols, X-MAC and PW-MAC, has weaknesses which generates too many control packets and has data collision problem between multiple transmitters, respectively. Therefore, we propose a receiver-initiated asynchronous MAC protocol which generates control packets from transmitter to complement these disadvantages. Compared to the prior asynchronous duty cycling approaches of X-MAC and PW-MAC, the proposed protocol shows a improvement in energy-efficiency, throughput and latency from simulation results.

Design of Corrective Controllers for Model Matching of Switched Asynchronous Sequential Machines (스위칭 비동기 순차 머신을 위한 모델 정합 교정 제어기 설계)

  • Yang, Jung-Min
    • Journal of Korean Institute of Intelligent Systems
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    • v.25 no.2
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    • pp.139-146
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    • 2015
  • This paper presents the solution to model matching of switched asynchronous sequential machines by corrective control. We propose a model of switched asynchronous sequential machines, in which the system can have different dynamics of asynchronous machines governed by a pre-determined sequence of switching. The control objective is to derive a corrective control law so that the stable state behavior of the closed-loop system can match that of a prescribed model. A new skeleton matrix is defined to represent the reachability of the switched asynchronous machine, and a novel control scheme is presented that interweaves the switching signal and the corrective control procedure. A design algorithm for the proposed controller is illustrated in a case study.

A synchronized processing algorithm of asynchronous data with trigger (트리거를 이용한 비동기 데이터의 동기화 처리 알고리즘 연구)

  • 박성진;유지상
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.12A
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    • pp.1002-1008
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    • 2003
  • In terrestrial data broadcasting, we are just on the beginning stage in all aspects including implementation and design techniques and only asynchronous data processing has been receiving a little study. In this paper, we therefore propose an efficient processing algorithm for synchronization of asynchronous data by using trigger information to make more diverse service possible with a variety of contents. In the proposed algorithm, trigger data is encapsulated in DSM-CC section and transmitted in a form of MPEG-2 TS. The data is then separated in PC type set-top box and detached asynchronous data and trigger data are stored by the proposed algorithm. Pre-loaded asynchronous data is displayed when STC(system time clock) has the same value as PTS(presentation time stamp). Proper operation of the proposed algorithm was verified by using a content of asynchronous data with extensible markup language(XML) and a declarative application(DA) browser.

Asynchronous Cache Invalidation Strategy to Support Read-Only Transaction in Mobile Environments (이동 컴퓨팅 환경에서 읽기-전용 트랜잭션을 지원하기 위한 비동기적 캐쉬 무효화 기법)

  • Kim, Il-Do;Nam, Sung-Hun
    • The KIPS Transactions:PartC
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    • v.10C no.3
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    • pp.325-334
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    • 2003
  • In stateless server, if an asynchronous cache invalidation scheme attempts to support local processing of read-only transaction in mobile client/sever database systems, a critical problem may occur ; the asynchronous invalidation reports provide no guarantees of waiting time for mobile transactions requesting commit. To solve this problem, the server in our algorithm broadcasts two kind of messages, asynchronous invalidation report to reduce transaction latency and periodic guide message to avoid the uncertainty of waiting time for the next invalidation report. The asynchronous invalidation report has its own sequence number and the periodic guide message has the sequence number of the most recently broadcast asynchronous invalidation report. A mobile client checks its cache validity by using the sequence numbers of these messages.

Fault Diagnosis and Tolerance for Asynchronous Counters with Critical Races Caused by Total Ionizing Dose in Space (우주 방사능 누적에 의한 크리티컬 레이스가 존재하는 비동기 카운터를 위한 고장 탐지 및 극복)

  • Kwak, Seong-Woo;Yang, Jung-Min
    • Journal of Korean Institute of Intelligent Systems
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    • v.22 no.1
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    • pp.49-55
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    • 2012
  • Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

Instruction-level Power Model for Asynchronous Processor (명령어 레벨의 비동기식 프로세서 소비 전력 모델)

  • Lee, Je-Hoon
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.7
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    • pp.3152-3159
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    • 2012
  • This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.