• Title, Summary, Keyword: Asynchronous

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Automatic STG Derivation with Consideration of Special Properties of STG-Based Asynchronous Logic Synthesis (신호전이그래프에 기반한 비동기식 논리합성의 고유한 특성을 고려한 신호전이그래프의 자동생성)

  • Kim, Eui-Seok;Lee, Jeong-Gun;Lee, Dong-Ik
    • The KIPS Transactions:PartA
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    • v.9A no.3
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    • pp.351-362
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    • 2002
  • Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

Self-Power Gating Technique For Low Power Asynchronous Circuit

  • Mai, Kim-Ngan Thi;Vo, Huan Minh
    • Journal of IKEEE
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    • v.22 no.3
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    • pp.548-557
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    • 2018
  • In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

Design of Asynchronous Library and Implementation of Interface for Heterogeneous System

  • Jung, Hwi-Sung;Lee, Joon-Il;Lee, Moon-Key
    • Proceedings of the IEEK Conference
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    • pp.221-225
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    • 2000
  • We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

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The Performance Potential of Data Dependent Computation on Asynchronous Superscalar Processor

  • Kim, Suk-Jin;Park, Byung-Soo;Park, Chan-Ho;Lee, Dong-Ik
    • Proceedings of the IEEK Conference
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    • pp.414-416
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    • 2000
  • We investigate potential advantages and problems when a superscalar processor is designed and implemented using asynchronous design methods. Conventional techniques of superscalar processing are applied and data dependent adder is considered as an asynchronous component. Intensive simulations on SPEC INT95 benchmark suites are made for the purpose of performance comparison between a synchronous and an asynchronous superscalar processor, respectively. The simulation results show about 5% speedup with asynchronous design methods in the sense of Issue Rate.

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A Study on the Interface Circuit Creation Algorithm using the Flow Chart (흐름도를 이용한 인터페이스 회로 생성 알고리즘에 관한 연구)

  • 우경환;이천희
    • Journal of the Korea Society for Simulation
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    • v.10 no.1
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    • pp.25-34
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    • 2001
  • In this paper, we describe the generation method of interface logic which replace between IP & IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new asynchronous sequential "Waveform to VHDL" code creation algorithm by flow chart conversion : Wave2VHDL - if only mixed asynchronous timing waveform is presented the level type input and pulse type input for handshaking, we convert waveform to flowchart and then replace with VHDL code according to converted flowchart. Also, we confirmed that asynchronous electronic circuits are created by applying extracted VHDL source code from suggest algorithm to conventional domestic/abroad CAD Tool, Finally, we assured the simulation result and the suggest timing diagram are identical.

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Energy-Saving Oriented On/Off Strategies in Heterogeneous Networks : an Asynchronous Approach with Dynamic Traffic Variations

  • Tang, Lun;Wang, Weili;Chen, Qianbin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.11
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    • pp.5449-5464
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    • 2018
  • Recent works have validated the possibility of reducing the energy consumption in wireless heterogeneous networks, achieved by switching on/off some base stations (BSs) dynamically. In this paper, to realize energy conservation, the discrete time Markov Decision Process (DTMDP) is developed to match up the BS switching operations with the traffic load variations. Then, an asynchronous decision-making algorithm, which is based on the Bellman equation and the on/off priorities of the BSs, is firstly put forward and proved to be optimal in this paper. Through reducing the state and action space during one decision, the proposed asynchronous algorithm can avoid the "curse of dimensionality" occurred in DTMDP frequently. Finally, numerical simulations are conducted to validate the effectiveness and advantages of the proposed asynchronous on/off strategies.

On Relationship between Safety and Liveness of Election Problem in Asynchronous Distributed Systems

  • Park, Sung-Hoon
    • International Journal of Contents
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    • v.7 no.4
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    • pp.30-34
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    • 2011
  • A Leader is a Coordinator that supports a set of processes to cooperate a given task. This concept is used in several domains such as distributed systems, parallelism and cooperative support for cooperative work. In completely asynchronous systems, there is no solution for the election problem satisfying both of safety and liveness properties in asynchronous distributed systems. Therefore, to solve the election problem in those systems, one property should be weaker than the other property. If an election algorithm strengthens the safety property in sacrifice of liveness property, it would not nearly progress. But on the contrary, an election algorithm strengthening the liveness property in sacrifice of the safety property would have the high probability of violating the safety property. In this paper, we presents a safety strengthened Leader Election protocol with an unreliable failure detector and analyses it in terms of safety and liveness properties in asynchronous distributed systems.

Model Matching of Asynchronous Sequential Machines with Input Disturbance (입력 외란이 존재하는 비동기 순차 머신의 모델 매칭)

  • Yang, Jung-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.1
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    • pp.109-116
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    • 2008
  • Model matching problem of asynchronous sequential machines is addressed in this paper. The main topic is to design a corrective controller such that the closed-loop behavior of the asynchronous sequential machine can follow a given model, i.e., their models can be "matched" in stable states. In particular, we assume that the considered asynchronous machine suffers from the presence of an input disturbance that can cause undesirable state transitions. The proposed controller can realize both model matching and elimination of the adverse effect of the input disturbance. Necessary and sufficient condition for the existence of a corrective controller that solves model matching problem is presented. Whenever controller exists, algorithms for their design are outlined and demonstrated in a case study.

A High Performance Asynchronous Interface Unit for Globally-Asynchronous Locally-Synchronous Systems (전역적 비동기 지역적 동기 시스템을 위한 고성능 비동기식 접속장치)

  • 오명훈;박석재;최호용;이동익
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.5
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    • pp.321-334
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    • 2003
  • Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

Statistically Optimized Asynchronous Barrel Shifters for Variable Length Codecs (통계적으로 최적화된 비동기식 가변길이코덱용 배럴 쉬프트)

  • Peter A. Beerel;Kim, Kyeoun-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.11A
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    • pp.891-901
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    • 2003
  • This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.