• Title, Summary, Keyword: Asynchronous

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Corrective Control of Asynchronous Sequential Machines with Input Disturbance I : Modeling (입력 외란이 존재하는 비동기 순차 머신의 교정 제어 I : 모델링)

  • Yang, Jung-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.9
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    • pp.1655-1664
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    • 2007
  • This paper presents the problem of controlling asynchronous sequential machines in the presence of input disturbances, which may be also regarded as an adversary in a game theoretic setting. The main objective is to develope a new methodology for including unpredictable behavior of input disturbance into models of asynchronous machines. The input disturbance, representing uncontrollable noise input, is embedded into a new model of asynchronous machines in form of input/state finite state machines. It is shown that the proposed modeling preserves the fundamental model and well-pose of asynchronous machines. The reachability matrix, an important performance index of asynchronous machines, is also adapted according to input disturbance and will be used for constructing corrective controllers in the companion paper.

Architectural Design Issues in a Clockless 32-Bit Processor Using an Asynchronous HDL

  • Oh, Myeong-Hoon;Kim, Young Woo;Kwak, Sanghoon;Shin, Chi-Hoon;Kim, Sung-Nam
    • ETRI Journal
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    • v.35 no.3
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    • pp.480-490
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    • 2013
  • As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

A Study on the Detection of Asynchronous State of the Synchronous Generator

  • Choi, Hyung-Joo;Lee, Heung-Ho
    • Journal of international Conference on Electrical Machines and Systems
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    • v.2 no.4
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    • pp.405-412
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    • 2013
  • This paper includes new protection concepts and practices to avoid mechanical damage of three-phase transformer by asynchronous operation of synchronous generator. this failure is often caused just after synchronous generator was connected to the grid because of a malfunction of the controller or misconnections of the synchronous devices. The results of the studies on the analyzing the phenomenon of asynchronous operation experienced in Korea and rapidly detecting asynchronous state are descrived.

Transient Coordinator: a Collision Resolution Algorithm for Asynchronous MAC Protocols in Wireless Sensor Networks

  • Lee, Sang Hoon;Park, Byung Joon;Choi, Lynn
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.6 no.12
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    • pp.3152-3165
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    • 2012
  • Wireless sensor networks (WSN) often employ asynchronous MAC scheduling, which allows each sensor node to wake up independently without synchronizing with its neighbor nodes. However, this asynchronous scheduling may not deal with collisions due to hidden terminals effectively. Although most of the existing asynchronous protocols exploit a random back-off technique to resolve collisions, the random back-off cannot secure a receiver from potentially repetitive collisions and may lead to a substantial increase in the packet latency. In this paper, we propose a new collision resolution algorithm called Transient Coordinator (TC) for asynchronous WSN MAC protocols. TC resolves a collision on demand by ordering senders' transmissions when a receiver detects a collision. To coordinate the transmission sequence both the receiver and the collided senders perform handshaking to collect the information and to derive a collision-free transmission sequence, which enables each sender to exclusively access the channel. According to the simulation results, our scheme can improve the average per-node throughput by up to 19.4% while it also reduces unnecessary energy consumption due to repetitive collisions by as much as 91.1% compared to the conventional asynchronous MAC protocols. This demonstrates that TC is more efficient in terms of performance, resource utilization, and energy compared to the random back-off scheme in dealing with collisions for asynchronous WSN MAC scheduling.

Corrective Control of Asynchronous Sequential Circuits with Faults from Total Ionizing Dose Effects in Space (총이온화선량에 의한 고장이 존재하는 비동기 순차 회로의 교정 제어)

  • Yang, Jung-Min;Kwak, Seong-Woo
    • Journal of Institute of Control, Robotics and Systems
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    • v.17 no.11
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    • pp.1125-1131
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    • 2011
  • This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.

Corrective Control of Input/Output Asynchronous Sequential Machines for Overcoming Disturbance Inputs (외란 입력을 극복하기 위한 입력/출력 비동기 머신의 교정 제어)

  • Yang, Jung-Min;Kwak, Seong-Woo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.3
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    • pp.591-597
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    • 2009
  • The problem of controlling a finite-state asynchronous sequential machine is examined. The considered machine is governed by input/output control, where access to the state of the machine is not available. In particular, disturbance inputs can infiltrate into the asynchronous machine and provoke unauthorized state transitions. The control objective is to use output feedback to compensate the machine so that the closed-loop system drive the faulty asynchronous machine from a failed state to the original one. Necessary and sufficient condition for the existence of appropriate controllers are presented in a theoretical framework. As a case study, the closed-loop system of an asynchronous machine with the proposed control scheme is implemented in VHDL code.

Design Technique of Register-based Asynchronous FIFO (레지스터 기반 비동기 FIFO 구조 설계 기법)

  • Lee, Yong-Hwan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.1038-1041
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    • 2005
  • In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

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Asynchronous State Feedback Control for SEU Mitigation of TMR Memory (비동기 상태 피드백 제어를 이용한 TMR 메모리 SEU 극복)

  • Yang, Jung-Min;Kwak, Seong-Woo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.8
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    • pp.1440-1446
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    • 2008
  • In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

Error Analysis of the Navigation System with Asynchronous Gyros

  • Kim, Kwang-Jin;Lee, Tae-Gyoo
    • 제어로봇시스템학회:학술대회논문집
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    • pp.177.2-177
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    • 2001
  • The asynchronous gyro outputs in the 3-axis navigation system are defined as each of gyros has its own output frequency. In this case, the navigation system has gyro outputs concurrently with the sensor mechanical frequency instead of the attitude frequency. So, there is an asynchronous error between gyro outputs and attitude calculation. In this paper, we analyze the gyro output error caused by the asynchronous gyro and present the high speed sampling technique and the extrapolation and interpolation of gyro outputs for synchronizing the gyro outputs.

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Fine-Grain Pipeline Control Circuit for High Performance Microprocessors (고성능 마이크로프로세서를 위한 파이프라인 제어로직)

  • 배상태;김홍국
    • Proceedings of the Korean Information Science Society Conference
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    • pp.931-933
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    • 2004
  • In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25$\mu\textrm{m}$ technology indicates 17% lower latency than GasP.

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