- Volume 39 Issue 4
DOI QR Code
Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems
- Oh, Myeong-Hoon (SW & Contents Research Laboratory, ETRI and the Department of Computer Software, University of Science and Technology (UST)) ;
- Kim, Young Woo (SW & Contents Research Laboratory, ETRI and the Department of Computer Software, University of Science and Technology (UST)) ;
- Kim, Hag Young (SW & Contents Research Laboratory, ETRI) ;
- Kim, Young-Kyun (SW & Contents Research Laboratory, ETRI) ;
- Kim, Jin-Sung (Department of Electronic Engineering, Sun Moon University)
- Received : 2016.08.11
- Accepted : 2017.05.22
- Published : 2017.08.01
To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using
Grant : Low-power and High-density Micro Server System Development for Cloud Infrastructure
Supported by : Institute for Information & communications Technology Promotion(IITP)
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