DOI QR코드

DOI QR Code

Compact Current Model of Single-Gate/Double-Gate Tunneling Field-Effect Transistors

  • Yu, Yun Seop (Dept. of Electrical, Electronic and Control Electronic Engineering and IITC, Hankyong National University) ;
  • Najam, Faraz (Dept. of Electrical, Electronic and Control Electronic Engineering and IITC, Hankyong National University)
  • Received : 2017.03.07
  • Accepted : 2017.04.27
  • Published : 2017.09.01

Abstract

A compact current model applicable to both single-gate (SG) and double-gate (DG) tunneling field-effect transistors (TFETs) is presented. The model is based on Kane's band-to-band tunneling (BTBT) model. In this model, the well-known and previously-reported quasi-2-D solution of Poisson's equation is used for the surface potential and length of the tunneling path in the tunneling region. An analytical tunneling current expression is derived from expressions of derivatives of local electric field and surface potential with respect to tunneling direction. The previously reported correction factor with three fitting parameters, compensating for superlinear onset and saturation current with drain voltage, is used. Simulation results of the proposed TFET model are compared with those from a technology computer-aided-design (TCAD) simulator, and good agreement in all operational bias is demonstrated. The proposed SG/DG-TFET model is developed with Verilog-A for circuit simulation. A TFET inverter is simulated with the Verilog-A SG/DG-TFET model in the circuit simulator; the model exhibits typical inverter characteristics, thereby confirming its effectiveness.

Keywords

Compact model;Band-to-band tunneling (BTBT);Surface potential;Tunneling field-effect-transistor (TFET)

Acknowledgement

Supported by : Ministry of Trade, Industry & Energy (MOTI), Korea Semiconductor Research Consortium(KSRC), IDEC (EDA Tool)

References

  1. H. Lu and A. Seabaugh, "Tunnel field-effect transistors: State-of-the-art," IEEE J. Electron Devices Soc., vol. 2, no. 4, pp.44-49, Apr. 2014. https://doi.org/10.1109/JEDS.2014.2326622
  2. A. M. Ionescu and H. Riel, "Tunnel field-effect transistors as energy efficient electronic switches," Nature, vol. 479, no. 7373, pp. 329-337, Nov. 2011. https://doi.org/10.1038/nature10679
  3. Q. Huang, R. Jia, C. Chen, H. Zhu, L. Guo, J. Wang, J. Wang, C. Wu, R. Wang, W. Bu, J. Kang, W. Wang, H. Wu, S.-W. Lee, Y. Wang, and R. Huang, "First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap," in Proc. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC, USA, Dec. 2015, pp. 22.2.1-22.2.4, doi: 10.1109/IEDM.2015.7409756. https://doi.org/10.1109/IEDM.2015.7409756
  4. M. Lanuzza, S. Strangio, F. Crupi, P. Palestri, and D. Esseni, "Mixed Tunnel-FET/MOSFET Level Shifters: a new proposal to extend the Tunnel-FET application domain," IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 3973-3979, Dec. 2015. https://doi.org/10.1109/TED.2015.2494845
  5. D. H. Morris, U. E. Avci, R. Rios, and I. A. Young, "Design of low voltage tunneling-FET logic circuits considering asymmetric conduction characteristics," IEEE J. Emerg. Sel. Topics Circuits Syst., vol. 4, no. 4, pp. 380-388, Dec. 2014. https://doi.org/10.1109/JETCAS.2014.2361054
  6. M. G. Bardon, H. P. Neves, R. Puers, and C. V. Hoof, "Pseudo two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions," IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 827-834, Apr. 2010. https://doi.org/10.1109/TED.2010.2040661
  7. Y. Hong, Y. Yang, L. Yang, G. Samudra, C. H. Heng, and Y. C. Yeo, "SPICE behavioral model of the tunneling field-effect transistor for circuit simulation," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 12, pp. 946-950, Dec. 2009. https://doi.org/10.1109/TCSII.2009.2035274
  8. H. Lu, D. Esseni, and A. Seabaugh, "Universal analytic model for tunnel FET circuit simulation," Solid-State Electronics, vol. 108, pp. 110-117, 2015. https://doi.org/10.1016/j.sse.2014.12.002
  9. L. Zhang and M. Chan, "SPICE modeling of doublegate tunnel-FETs including channel transports," IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 300-307, Feb. 2014. https://doi.org/10.1109/TED.2013.2295237
  10. M. Gholizadeh and S. E. Hosseini, "A 2-D analytical model for double gate tunnel FETs," IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1494-1500, May 2014. https://doi.org/10.1109/TED.2014.2313037
  11. A. Pan and C. O. Chui, "A quasi-analytical model for double-gate tunneling field-effect transistors," IEEE Electron Device Lett., vol. 33, no. 10, pp. 1468-1470, Oct. 2012. https://doi.org/10.1109/LED.2012.2208933
  12. C. Wu, R. Huang, Q. Huang, C. Wang, J. Wang, and Y. Wang, "An analytical surface potential model accounting for the dual-modulation effects in tunnel FETs," IEEE Trans. Electron Devices, vol. 61, no. 8, pp. 2690-2696, Aug. 2014. https://doi.org/10.1109/TED.2014.2329372
  13. A. Pal and A. K. Dutta, "Analytical Drain Current Modeling of Double-Gate Tunnel Field-Effect Transistors," IEEE Trans. Electron Devices, vol. 63, no. 8, pp. 3213-3221, Aug. 2016. https://doi.org/10.1109/TED.2016.2581842
  14. E. O. Kane, "Zener tunneling in semiconductors," J. Phys. Chem. Solids, vol. 12, no. 2, pp. 181-188, Jan. 1960. https://doi.org/10.1016/0022-3697(60)90035-4
  15. A. S. Verhulst, D. Leonelli, R. Rooyackers, and G. Groeseneken, "Drain voltage dependent analytical model of tunnel field-effect transistors," J. Appl. Phys., vol. 110, no. 2, pp. 024510-1-024510-10, Jul. 2011. https://doi.org/10.1063/1.3609064
  16. SmartSpice Manual Ver. 4.18.16.R, SILVACO International, Santa Clara, CA, 2015.
  17. ATLAS Manual Ver. 5.20.2.R, SILVACO International, Santa Clara, CA, 2015.
  18. H. Xu, Y. Dai, N. Li, and J. Xu, "A 2-D semianalytical model of double-gate tunnel field-effect transistor," J. Semicond., vol. 36, no. 5, pp. 1-7, May 2015.
  19. S. F. Najam, M. L. B. Tan, and Y. S. Yu, "General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors," J. lnf. Commun. Converg. Eng., vol. 11, no. 1, pp. 115-121, Mar. 2016, doi:10.6109/jicce.2016.14.2.115. https://doi.org/10.6109/jicce.2016.14.2.115