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Metastability Window Measurement of CMOS D-FF Using Bisection

이분법을 이용한 CMOS D-FF의 불안정상태 구간 측정

  • 김강철 (전남대학교 컴퓨터공학과) ;
  • Received : 2016.11.07
  • Accepted : 2017.04.24
  • Published : 2017.04.30

Abstract

As massive integration technology of transistors has been developing, multi-core circuit is fabricated on a silicon chip and a clock frequency is getting faster to meet the system requirement. But increasing the clock frequency can induce some problems to violate the operation of system such as clock synchronization, so it is very import to avoid metastability events to design digital chips. In this paper, metastability windows are measured by bisection method in H-spice depending on temperature, supply voltage, and the size of transmission gate with D-FF designed with 180nm CMOS process. The simulation results show that the metastability window(: MW) is slightly increasing to temperature and supply voltage, but is quadratic to the area of a transmission gate, and the best area ration of P and Ntransitor in transmission gate is P/N=4/2 to get the least MW.

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