Design of High-performance Parallel BCH Decoder for Error Collection in MLC Flash Memory

MLC 낸드 플래시 메모리 오류정정을 위한 고속 병렬 BCH 복호기 설계

  • 최원정 (강원대학교 공학대학 전자정보통신공학과) ;
  • 이제훈 (강원대학교 공학대학 전자정보통신공학부) ;
  • 성원기 (강원대학교 공학대학 전자정보통신공학부)
  • Received : 2016.01.05
  • Accepted : 2016.02.06
  • Published : 2016.03.28


This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.


Supported by : 강원대학교, 한국연구재단


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