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A Design of FPGA Self-test Circuit Reusing FPGA Boundary Scan Chain

FPGA 경계 스캔 체인을 재활용한 FPGA 자가 테스트 회로 설계

  • Yoon, Hyunsik (Department of Computer Engineering, Hanbat National University) ;
  • Kang, Taegeun (Department of Computer Engineering, Hanbat National University) ;
  • Yi, Hyunbean (Department of Computer Engineering, Hanbat National University)
  • 윤현식 (한밭대학교 컴퓨터공학과) ;
  • 강태근 (한밭대학교 컴퓨터공학과) ;
  • 이현빈 (한밭대학교 컴퓨터공학과)
  • Received : 2015.03.25
  • Accepted : 2015.05.31
  • Published : 2015.06.25

Abstract

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

Acknowledgement

Supported by : 한국연구재단

References

  1. Sony Corporation, Sony Semiconductor Quality and Reliability Handbook, 1st edition, Oct 2000.
  2. Renesas Electronics, Semiconductor Reliability Handbook, Rev.1.01, Nov 2008.
  3. Y. Park, I. Choi, and S. Kang, "IEEE std. 1500 based an Efficient Programmable Memory BIST," Journal of The Institute of Electronics Engineers of Korea, Vol. 50, NO. 2, pp. 114-121, Feb 2013.
  4. Y. Kim, I. Kim, and H. Min, "BIST structure based on new Random Access Scan architecture for Low Power Scan Test," ITC-CSCC, pp. 812-815, July 2009.
  5. "IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices", Application Note, no. 39, June 2005.
  6. M. Abramovici, C. Stroud, C. Hamilton, S. Wijesuriya, and V. Verma, "Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications," Int. Test Conf.(ITC), pp. 973-982, 1999.
  7. C. Hsu, and T. Chen, "Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA," IEEE Trans. on Instrumentation and Measurement, Vol. 58, Issue. 7, pp. 2300-2315, Feb 2009. https://doi.org/10.1109/TIM.2009.2013921
  8. P. Gadde, and M. Niamat, "FPGA Memory Testing Technique using BIST," IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), pp. 473-476, Aug 2013.
  9. N. Das, P. Roy, and H. Rahaman, "Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate array," IET, on Computers & Digital Techniques, Vol. 7, No. 5, pp. 210-220, Sep 2013. https://doi.org/10.1049/iet-cdt.2012.0111
  10. S. Vemula, and C. Stroud, "Built-in self-test for programmable I/O buffers in FPGAs and SoCs," IEEE Southeastern Symp. on System Theory, pp. 534-538, Mar 2006.
  11. S. Rehman, M. Benabdenbi, and L. Anghel, "BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA," IEEE Int. Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 296-301, Oct 2013.
  12. K. Ito, T. Yoneda, Y. Yamato, K. Hatayama, and M. Inoue, "Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test," IEICE Tech. Vol. 113, no. 353, pp. 1-6, 2013.