A Design of FPGA Self-test Circuit Reusing FPGA Boundary Scan Chain

FPGA 경계 스캔 체인을 재활용한 FPGA 자가 테스트 회로 설계

  • Yoon, Hyunsik (Department of Computer Engineering, Hanbat National University) ;
  • Kang, Taegeun (Department of Computer Engineering, Hanbat National University) ;
  • Yi, Hyunbean (Department of Computer Engineering, Hanbat National University)
  • 윤현식 (한밭대학교 컴퓨터공학과) ;
  • 강태근 (한밭대학교 컴퓨터공학과) ;
  • 이현빈 (한밭대학교 컴퓨터공학과)
  • Received : 2015.03.25
  • Accepted : 2015.05.31
  • Published : 2015.06.25


This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.


Supported by : 한국연구재단


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