# NOMENCLATURE

# I. INTRODUCTION

In grid-connected inverters (Fig. 1), classical proportional-integrator (PI) controllers suffer from relatively low loop gains at the fundamental frequency and the corresponding harmonics. As a result, the inverters that use these types of controllers tend to have poor grid harmonic disturbance rejections, which result in poor output current Total Harmonic Distortion (THD) if the grid voltage is heavily distorted. Different controllers and topologies have been proposed (e.g., [1]-[4]) to provide high-quality output currents that comply with national and international standards [5], [6]. Proportional-resonant (PR) controllers have also been widely used [7]-[13]. Theoretically, a PR controller has infinite gain at selected frequencies. Accurate tracking of the demanded current waveform can be achieved through having multiple PR controllers tuned at the fundamental frequency and its main harmonics. However, implementing such a controller in practice is complicated.

**Fig. 1.**Grid-connected inverter.

Repetitive control (RC) is widely used in many practical industrial systems, such as manufacturing [14], disk drives [15], and robotics [16]. RC has also been used in power electronics, such as uninterruptible power supplies [17], [18], active filters [19]-[21], DC/DC converters [22], [23], and grid-connected inverters [24], [25]. These controllers are based on the concept of iterative learning control, and error between the reference and the output over one fundamental cycle is used to generate a new reference for the next fundamental cycle. RC is mathematically equivalent to a parallel combination of numerous resonant controllers, an integral controller, and a proportional controller [26]. Therefore, it is as effective as a PR controller at producing high-quality output currents in a grid-connected inverter, with the added advantage of being simpler and easier to implement. However, the performance of both PR and RC deteriorates significantly when the grid frequency deviates from the nominal value, because high-resonant gains will not match the fundamental frequency and the grid harmonics.

The frequency output from a phase-locked loop (PLL) can be used as input in PR controllers to have adaptive tuning with respect to the grid frequency, as suggested in [12] and [13]. However, all controller parameters must be adaptive, which makes the practical implementation of such mechanisms complicated, especially when a bank of resonant controllers is used to reject a high number of harmonics. Non-ideal PR controllers provide good immunity to variation in grid frequencies by widening resonant peaks at the expense of reducing the gains of the peaks. This phenomenon reduces the effectiveness of the controllers in tracking the demanded waveform [7].

The voltage control of grid-connected inverters with a frequency adaptive mechanism based on H∞ repetitive control was proposed in [24] and [25]. The internal model of the system consists of a delay unit e-TDs that is cascaded with a low-pass filter, W(s) = ωc/s + ωC. The adaptive mechanisim is based on varying the cut-off frequency of the filter ωC according to the varying grid frequency. According to the authors, this mechanism is effective for a grid frequency variation of only ±0.2 Hz. If the grid variation is higher than this limit, then the controller delay TD must be changed. However, implementing an adaptive delay is impossible for low-sampling frequencies without further deterioration of the controller performance [24].

To overcome the deficiencies of conventional RC, this paper proposes an odd-harmonic frequency adaptive repetitive controller (ARC) for a grid-connected inverter suitable for implementation in a digital signal processor (DSP). The frequency adaptive feature is based on varying both switching and sampling frequencies according to the grid frequency, thus keeping the number of RC delay samples constant. This mechanism can precisely track changes in the grid frequency and keep the high-resonant gains lined up with the grid harmonics. The design procedure of the controller is explained in detail, and the practical DSP implementation of the proposed controller is also discussed. The performance of the proposed controller is compared to that of a PR controller and is found to be superior.

# II. CONTROLLER S TRUCTURE AND SYSTEM MODELING

Fig. 1 shows the circuit diagram of a conventional two-level, grid-connected inverter with an LCL filter. The inverter parameters used in this study are listed in Table I. Fig. 2 shows the block diagram that represents the control scheme implemented in each phase. The controller consists of an outer loop of the output current and an inner loop of the capacitor current to provide active damping. This structure increases the degree of freedom in designing the controller compared with the widely used one-feedback loop of L1 current, because two controller gains (KC and K) can be optimized instead of only one controller gain. A plug-in repetitive controller transfer function (GRC ) is implemented to reject the current harmonics that the grid voltage harmonics caused. The repetitive controller can reject the disturbance of the fundamental harmonic and its multiples. However, the convergence time of the repetitive controller is relatively long. Thus, a feedforward loop of the fundamental nominal component of the grid voltage is implemented to reduce the current error during the convergence time of the RC, which will be explained later. The controller in Fig. 2 has the form of K + GR(Z) which means that it is proportional plus repetitive controller but it will be simply abbreviated as RC in this paper.

**Table I**INVERTER PARAMETERS

**Fig. 2.**Block diagram of one phase and its controller.

The block diagram of Fig. 2 can be simplified, as shown in Fig. 3(a). The transfer functions that appear in Fig. 3(a) are given by

From Fig. 3a, Vg (s)B(s) represents the disturbance that the grid voltage caused. Two options are available to reject this disturbance: RC and feedforward. Using RC to deal with grid disturbance at the fundamental frequency means that at least one fundamental cycle (or half fundamental cycle in case of an odd-harmonic RC) delay will occur for the controller to feed the error that one fundamental cycle created back to the system for the next cycle. However, the error that the fundamental component of the grid voltage caused will be high and the inverter may generate a current several times the reference current during the first cycle. Considering the feedforward option, and to completely compensate for the grid disturbance, the feedforward loop should ideally have the form of Vg (s)B(s), as seen in Fig. 3(a). The second derivative component L1Cs2 in Eq. (3) is small and can be neglected. Therefore, the feedforward of the component (1+ KCCs)Vg should effectively reject grid disturbance. However, this action involves the differentiation of the grid voltage signal, which is undesirable in practice because of noise amplification.

**Fig. 3.**Block diagram. (a) One phase and its controller. (b) Simplified block diagram.

To avoid differentiation in the feedforward and overcome the long delay of the RC, the proposed strategy involves using the feedforward to compensate for the disturbance that the fundamental frequency caused using a pre-known value of the nominal grid voltage and relying on the RC to compensate for the disturbance that all the other harmonics caused. Using the known nominal value of the grid rms voltage Vgo and frequency fgo, the feedforward component that compensates for the fundamental component according to Eq. (3) (neglecting L1Cs2) is given in the following equation:

If the grid voltage is slightly different from its nominal value, the RC will compensate for the current error caused by this difference.

With a fully discretized system, Fig. 3(a) can be further simplified as Fig. 3(b). The disturbance Dg (z) represents any grid disturbance that has not been compensated using the feedforward Vf. The physical plant discretized transfer function Gp (z) can be calculated as

where G(z) and GH(z) are the Z-transforms of G(s) and G(s)H(s) respectively, given the Zero-Order-Hold (ZOH) method with sampling time Ts and computational time delay Td, such as

The transfer function of the odd-harmonic RC is given in [27] as

where Q(z) is a low-pass filter, KR is the RC gain, n is the number of samples in one fundamental cycle, and zm is a non-causal phase lead unit.

# III. SYSTEM ANALYSIS AND CONTROLLER DESIGN

The controller design involves the determination of KC, K, Q(z), KR, and m. From Fig. 3(b), the error signal E can be expressed as

Substituting Eq. (8) into Eq. (9) and rearranging gives

where

The block diagram in Fig. 4 can represent Eq. (10). This diagram consists of three cascaded transfer functions: T1(z), T2(z), and T3(z). T1(z) is the closed-loop transfer function without the repetitive controller, and stability can be guaranteed through choosing KC and K. The stability of the econd transfer function T2(z) can be guaranteed through choosing a stable low-pass filter Q(z). The stability of the third transfer function T3(z), which contains a positive feedback loop, can be guaranteed using the small gain theorem, i.e., the error signal will be bounded if the magnitude of the open-loop transfer function is less than 1 for all values of frequencies. Therefore,

**Fig. 4.**Block diagram of the system error.

## A. Selection of KC and K

If RC is not implemented, then the selection of the capacitor current loop gain KC and the output current loop gain K will be a compromise between good stability margins and good harmonics rejection; increasing KC will improve stability but will worsen harmonics rejection, whereas increasing K will worsen stability but will improve harmonics rejection [3]. In this study, the RC will handle harmonics rejection, and thus choosing KC and K is important to maximize the stability margins. The gains KC and K are chosen to provide good stability margins for T1 (z). Typical control system design criteria are used: phase margin between 40º to 70º and damping ratio from 0.3 to 0.7. The gains KC and K have been set to 5 and 3 respectively through analyzing Gp (z) in Matlab SISO Design Tool. This selection gives the following criteria: gain margin = 5.6 dB, phase margin = 51º, damping ratio ζ = 0.33, and settling time ts = 0.5 ms.

## B. Selection of Q(z)

The Bode diagram of the open-loop transfer function (K + GRC(z))Gp(z) with, Q(z) =1 is shown in Fig. 5. The system is unstable because of the resonant peaks near the crossover frequency, which means that Q(z) must be modified to attenuate the high-frequency peaks. A zero-phase low-pass filter is used, which has the following structure [28]:

Setting z = ejωTs (Ts is the sampling period) in Eq. (13) can obtain the frequency response of Q(z) as

Therefore,

From Eq. (15), the magnitude |Q(jωTs)| can be written as

In order to get a unity gain at zero frequency then αo and α1 must be chosen to satisfy αo + 2α1 = 1 to obtain a unity gain at zero frequency. αo and α1 must also be chosen to satisfy αo - 2α1 = 0 to obtain zero gain at high frequencies ωTs > π. Therefore, αo and α1 are set to 0.5, and 0.25, respectively. For the full frequency range, |Q(ejωTs)| is given through

The filter is now given through

The Bode diagram of Q(e jωTs), as described in Eq. (17), is shown in Fig. 6. The Bode diagram of the open-loop transfer function (K + GRC(z))Gp(z) with, Q(z), as described in Eq. (18), is shown in Fig. 7. This diagram confirms the stability of the system as the high gains near the crossover frequency are attenuated, and the system has positive stability margins.

**Fig. 5.**Bode diagram of the open-loop transfer function (K + GRC(z))Gp(z), with Q(z)=1, m=1, KR=0.5.

**Fig. 6.**Bode diagram of Q(z) = 0.25z+0.5+0.25z-1.

**Fig. 7.**Bode diagram of the open-loop transfer function (K + GRC(z))Gp(z), with Q(z)=0.25z+0.5+0.25z-1, m=1, KR=0.5 (GM=5.0dB, PM=44.1º)

## C. Selection of KR and m

The value of the RC gain KR must be carefully selected because it is a key parameter for error convergence and system stability. A high RC gain KR results in fast error convergence, but the feedback system becomes less stable. The non-causal phase lead unit of m is normally used to compensate for any delay or phase lag from the physical plant and controller transfer function. Implementing zm is not possible in practice unless zm is cascaded with the delay units of the KR. The design criterion used in this study maximizes K R to reduce RC convergence time while minimizing ||R(z)|| ∞ to increase stability margins. Fig. 8 shows the locus of vector |R(ejωTs)| for different values of KR when m = 3. As KR increases, the stability margin decreases until the system becomes unstable when KR > 4.8 because |R(ejωTs)| becomes greater than unity. In Fig. 9, ||R(z)|| ∞ is plotted against KR and m. For m = 0, the system is only stable when KR < 0.6 (||R(z)||∞ = 0.99 when KR = 0.6). This result indicates poor stability. Increasing m improves stability, and the best value is obtained when m = 3 because this value corresponds to the lowest possible ||R(z)||∞. The minimum value for ||R(z)||∞ occurs when KR = 2.8 and m = 3. These values were thus chosen for this design.

**Fig. 8.**Locus of the vector |R(ejωTs)|

**Fig. 9.**||R(z)|| ∞ versus KR and m.

# IV. FREQUENCY ADAPTIVE RC

In this section, a frequency adaptive RC is proposed to track the variations in grid frequency.

## A. Effect of grid frequency variation on RC performance

RC is equivalent to a parallel combination of resonant controllers with high gain at the fundamental frequency and its harmonics. It is implemented in this study to reject inverter output current harmonics that the presence of grid voltage harmonics causes. However, the grid frequency can vary with time because of the variation of loads or the connection or disconnection of large generators. Typically, grid frequency can oscillate by ±2%. Fig. 10 shows the Bode diagram of the open-loop transfer function of the system. The magnified portion of the diagram shows the resonant peak around the fifth harmonic. The benefit from this high gain occurs when the fifth harmonic is exactly 250 Hz. However, if the grid frequency changes by ±2%, the resonant peak will not align with the fifth harmonic and consequently the RC becomes ineffective. The linearized inverter model described in Fig. 2 is simulated in Matlab/Simulink with the PWM block set to unity gain. Some grid harmonics are included in the grid voltage Vg, and four causes are simulated for different grid frequencies fg. The simulation results of the output current after the RC converged are shown in Fig. 11. The performance of RC deteriorates dramatically when the grid frequency deviates from the nominal value. To remain effective, RC has to adapt to the varying grid frequency.

**Fig. 10.**Effect of grid frequency variation.

**Fig. 11.**Simulated output current for different grid frequencies.

## B. Proposed Frequency Adaptive Controller

The performance of the RC is not guaranteed unless the high-resonant gains align with the grid harmonics. Therefore, the time delay of the repetitive controller must adapt to the changes in the fundamental period of the grid voltage. The number of delay samples n can be changed with respect to the grid frequency. However, this mechanism will not result in a precise control of the time delay that RC used unless the switching frequency (and hence the sampling frequency) are high with respect to the fundamental frequency. For example, the number of samples per cycle is 4000/50 = 80 samples when the sampling frequency is 4 kHz, for a fundamental frequency of 50 Hz. Each sample is equivalent to 0.253 ms, which means that the minimum change in grid frequency this scheme can handle is approximately 0.63 Hz. According to the Bode diagram in Fig. 10, the RC gain at the fifth harmonic reduces by about 20% of the corresponding nominal value when the grid frequency deviates by only 0.15 Hz from the nominal value. For a 0.60 Hz deviation, the RC becomes completely ineffective. Fig. 11 also shows that the deterioration in RC performance begins to be noticeable when the grid frequency deviates by only 0.2 Hz from the nominal value. Therefore, varying the number of samples will not provide good tracking of the grid frequency without deteriorating the RC performance. The mechanism proposed in this study is to change the switching and sampling frequencies with respect to the grid frequency. The ratio of the sampling frequency to the fundamental frequency remains constant, and thus n does not need to change. Considering that the grid frequency can vary by up to ±2%, the sampling and switching frequencies can vary using the same ratio. Therefore, the switching frequency can vary from 7.84 kHz to 8.16 kHz. The attenuation of the LCL filter will change as the switching frequency varies within this range.

This mechanism benefits from the high precision of the DSP clock used to implement the controller. Fig. 12 shows the implementation of the PWM carrier in the DSP. In this study, the sampling frequency fs is set to twice the switching frequency, such as fs = 2 fsw. A counter based on the central processing unit (CPU) clock is set to count up and down periodically. The PWM counter period Ncpu is set to determine the required sampling period. Therefore,

where Ts and Tcpu are the sampling and CPU clock periods respectively. The number of samples n per fundamental cycle is given through

where Tg is the grid voltage fundamental period. The inverter modulating signal period is given using

Substituting Eq. (19) into Eq. (21) gives

According to Eq. (22), in order to vary the modulating signal period Tinv of the inverter, and hence the frequency finv, while maintaining n constant, the number of counts Ncpu should be changed.

**Fig. 12.**PWM implementation in the DSP.

Fig. 13 shows the proposed controller of the PWM counter period Ncpu. The grid voltage fundamental period Tg is sensed (using a PLL or zero crossing detector) and divided by nTcputo calculate the demand PWM counter period The period error EN is fed into a PI controller to calculate for, ΔNcpu, which is added to the nominal PWM counter period Ncpu_o to produce Ncpu. The nominal PWM counter period Ncpu_o is calculated in Eq. (23):

where Tso is the nominal switching period.

**Fig. 13.**PWM period control.

To highlight the advantage of this mechanism over changing n, we consider the case where the CPU frequency fcpu =150 MHz, n = 320, and the nominal switching frequency fso = 16 kHz. According to Eq. (23), the nominal PWM counter period Ncpu_o = 150 MHz/16 kHz = 9375. If the inverter modulating signal frequency finv is controlled through varying n, then when reducing n by 1 count, finv will be given by

However, if finv is controlled through varying Ncpu as proposed in this study, then when reducing Ncpu by 1 count, finv will be

Varying Ncpu gives 29 times more precision in controlling the frequency.

## C. Frequency Controller Design

According to most of the grid codes of practice, the grid frequency variation has a maximum slope of 1 Hz/s [12], which is nearly equivalent to an approximate 0.4 ms/s increase or decrease of grid period. The design objective is to track this variation and maintain the error signal between the PWM counter period Varying Ncpu and its demand to the minimum of one count. The deviation in grid frequency, and hence the PWM counter period demand , will be modeled as a ramp function:

where D is the rate of change of in count/s. From Fig. 13, the error EN (error signal between the PWM counter period Ncpu and its demand ) is given through the following equation:

The steady-state error ENss for a ramp input of can be calculated through substituting Eq. (26) into Eq. (27) and using the final-value theorem, such as

Maximum D is 184 count/s (equivalent to 0.4 ms/s). The integral gain ki is chosen to give the minimum possible steady-state frequency error, which is one count. Therefore ki is set to 184. The proportional gain kp is normally set to deal with transient response to a step input, In this case, a step change in grid frequency is unlikely and the proportional gain is set to 10.

## D. Effect of Varying Sampling Frequency on System Stability

Checking the effect of varying sampling frequencies on the stability of the repetitive controller is essential. Fig. 14 shows how ||R(z)||∞ varies for three different sampling frequencies that correspond to the nominal +2%, and -2% deviation in grid frequency. The effect of changing the sampling frequency on the stability of the ARC is minimal, and ||R(z)||∞ is inside the unit circle. The stabilities of T1 (z) and T1 (z) are not affected by varying the sampling frequency.

**Fig. 14.**Effect of different sampling frequencies on ||R(z)||∞, fs = 15.7, 16.0, and 16.3 kHz, KR=2.8, m=3.

# V. DESIGN OF A PROPORTIONAL RESONANT CONTROLLER

To compare the performance of the proposed ARC with other controllers reported in the literature, a PR controller is designed for the same inverter considered in this study. PR controller has been widely considered for its ability to reject harmonics by creating high-resonant peaks at specific frequencies. The ideal resonant controller is given in the following equation:

where ωh is the selected harmonic frequency that must be compensated, and Kh is the controller gain. Eq. (29) gives infinite gain at ωh. To avoid stability problems that may arise because of the infinite gain, a non-ideal resonant controller can be used as suggested in [7]:

where ωc is the cut-off frequency of the non-ideal resonant controller. The insertion of ωc reduces the resonant peaks and widens their bandwidth, causing the controller to be less sensitive to frequency variations. The use of several resonant controllers that are tuned to the desired odd-harmonic frequencies can create a resonant controller, such as

A bank of resonant controllers that are tuned to the low-order odd-harmonics up to H=19 is used. The design involves the determination of the cut-off frequency ωc and the controller gains Kh. A low value of ωc will make the controller sensitive to frequency variation and difficult to implement in a fixed point DSP [7], whereas a high value of ωc will reduce the resonant peaks and, hence, the controller performance. In practice, a ωc value of 5–15 rad/s is found to provide a good compromise [29]. In this design, ωc is set at 10 rad/s. The gains Kh are chosen to provide a good compromise between stability and performance. High gains will increase resonant peaks and thus improve harmonics rejection. However, the high gains will also left the open-loop Bode diagram up which will reduce the stability margins. The gains are set to reduce gradually as h increases so as to reduce the effect of the resonant peaks in the vicinity of the crossover frequency and thus reduce the effect on the stability margins. The gains Kh that were used are shown in Table II.

**Table II**PROPORTIONAL RESONANT CONTROLLER GAINS

The resonant controller is discretized using the bilinear Tustin transformation [30], such as

The PR controller is obtained through adding the proportional gain K to GRh(z). The Bode diagram of the open-loop transfer function (K + GRh(z))Gp(z) is shown in Fig. 15. The gain margin and the phase margin of this design are 2.5 dB and 21.0º respectively.

**Fig. 15.**Bode diagram of the open-loop transfer function (K + GRh(z))Gp(z), (GM = 2.5 dB, PM = 21.0º).

# VI. SIMULATION RESULTS

A detailed simulation model of the three-phase inverter is presented in Fig. 1, which was built using the MATLAB SimPowerSystems. The inverter parameters are listed in Table I. The grid voltage harmonics were measured in the laboratory, and similar values were included in the simulation model. The total grid voltage THD was measured to be 1.9%. The controller parameters for the RC and ARC used in the simulation are listed in Table III. The simulation parameters for the resonant controller are the same as the ones listed in Table II.

**Table III**CONTROLLER PARAMETERS

## A. Performance Comparison between P, PR, and RC at a Fixed Grid Frequency

In this section, a performance comparison is conducted between three different controllers: Proportional (P), PR, and RC. Fig. 16 shows the output current with the P controller for a 14A (rms) demand. The output current THD is 14.2%. The magnitude and phase angle of the 50 Hz fundamental component are 8.3A and -7.9º respectively. Fig. 17 shows the output current with the PR controller. The current THD is 2.6%. The magnitude and phase angle of the 50 Hz fundamental component are 13A and +8.0º respectively. Fig. 18 shows the output current with RC after the controller converged. The current THD is reduced to only 0.8%. The magnitude and phase angle of the 50 Hz fundamental component are 14A and -0.9º respectively. The effectiveness of the RC in improving the current THD and reference tracking is noticed. Fig. 19 shows the grid voltage harmonics used in the simulation model, and Fig. 20 shows the output current harmonics with P, PR, and RC.

**Fig. 16.**Simulated steady-state output current with only a proportional controller (THD = 14.2%).

**Fig. 17.**Simulated steady-state output current with PR (THD = 2.6%).

**Fig. 18.**Simulated steady-state output current with RC (THD = 0.8%).

**Fig. 19.**Grid voltage harmonics (percentage of fundamental).

**Fig. 20.**Output current harmonics (percentage of fundamental).

## B. Performance Comparison between PR, RC, and ARC at Varying Grid Frequencies

To test the effectiveness of the ARC, the grid frequency is set to change from 50 Hz to 50.2 Hz at the simulation time t = 0.1 s. The slope of change is 1 Hz/s. Fig. 21 shows the output current THD with PR, RC, and ARC. The THD is measured using a built-in Simulink block.

**Fig. 21.**Output current THD (Grid frequency started to change from 50 Hz to 50.2 Hz at t = 0.1s with a slope of 1 Hz/s).

With PR, the THD increased with frequency deviation and reached 3.5% before dropping to 2.8% when the grid frequency settled at 50.2 Hz. With RC, the current THD increased as the frequency deviation increased and reached 3.2%. Once the grid frequency reached 50.2 Hz and stopped deviating, the THD dropped to 1.8%. The ARC was able to keep the output current THD at 0.8% at all times.

Fig. 22 shows how the steady-state output current THD varies as the grid frequency deviates by ±2%. The PR is less sensitive to the variation in grid frequency than RC because PR has wider resonant peaks. The lowest THD with PR occurs at 49.8 Hz, not at 50.0 Hz, because of the quantization error of the discretization process. The superiority of ARC over PR and RC is clear because ARC can always keep the THD low regardless of the variation in grid frequency.

**Fig. 22.**Output current THD versus grid frequency.

# VII. PRACTICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS

The proposed RC was tested experimentally with the grid-connected inverter described in Fig. 1 and Table I. The control parameters are listed in Table III. The controller was implemented using a Texas Instrument TMS320F2812 32-bit fixed point DSP. The three-phase reference sine waves were generated internally through the DSP using lookup tables of n = 320 samples. The sine wave amplitude was set externally (using a setting in the user interface) and sent via Controller Area Network (CAN)-bus. The input DC was regulated using an external boost circuit to 700V dc, and thus the current could be injected into the 230 Vrms grid.

The RC controller was realized through programming as follows. From Eq. (8), the discrete transfer function that relates the RC output Y(z) to the RC input E(z) is given in the following equation:

Substituting Eq. (18) into Eq. (33) and rearranging gives

where X(z) is given in the following equation:

Eqs. (34) and (35) represent the indirect (standard) realization of digital controllers [30], which is represented in Fig. 23. The RC controller is implemented in a software through creating three arrays x(i) (one per phase), in which each is 160 (320/2) entries long. At the discrete time i, the RC output y(i) is calculated using the difference equation (36), and the array entry x(i) is filled using the difference equation (37)

where e(i) is the current error at discrete time i.

**Fig. 23.**RC Implementation.

A high-precision measurement of grid voltage frequency is required to implement the proposed frequency adaptive control. The grid voltage signal is sensed, and the Positive-Going Zero Crossing (PGZC) is detected. The fundamental period of the grid voltage Tg is measured through calculating the number of samples between two consecutive PGZCs.

To increase the measurement accuracy, the PGZC is detected every 15 fundamental cycles. In this way, the measurement error is reduced to Ts/15 (compared with Ts if the PGZC is detected every cycle). For the nominal sampling frequency of 16 kHz, the measurement error is only ±62.5 µs/15 = ±4.16 µs, which is equivalent to ±0.01 Hz.

Fig. 24 shows the output current when the RC is deactivated (i.e., proportional only controller P). The demand current is set to 15 A (rms). The current THD is measured to be 13.0%. Fig. 25 shows the output current when the RC is activated. The current THD is measured to be only 1.1%. Fig. 26 shows the measured output current harmonics with both P and RC.

**Fig. 24.**Output current without RC (10 A/div).

**Fig. 25.**Output current with RC (10 A/div).

**Fig. 26.**Experimental output current harmonics.

The grid frequency was monitored in the laboratory, and the maximum deviation recorded was ±0.1 Hz. The current THD was always maintained below 1.2%. To test the performance of the ARC against higher grid frequency deviation, an AC voltage source would need to be used to emulate the grid.

# VIII. CONCLUSION

The design and practical implementation of a frequency adaptive and odd-harmonic RC for a grid-connected inverter was discussed. The adaptive mechanism was found to be effective in tracking the changes in grid frequency and, therefore, in maintaining the effectiveness of the RC. The performance of the proposed controller was found to be superior to that of proportional resonant controller. The proposed mechanism presents a straightforward implementation using a DSP system.