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Gate Cost Reduction Policy for Direct Irreversible-to-Reversible Mapping Method without Reversible Embedding

가역 임베딩 없는 직접적 비가역-가역회로 매핑 방법의 게이트비용 절감 방안

  • 박동영 (강릉원주대학교 정보통신공학과) ;
  • 정연만 (강릉원주대학교 정보통신공학과)
  • Received : 2014.09.11
  • Accepted : 2014.11.10
  • Published : 2014.11.30

Abstract

For the last three decades after the advent of the Toffoli gate in 1980, while many reversible circuit syntheses have been presented reversible embedding methods onto suitable reversible functions, only a few proposed direct irreversible-to-reversible mapping methods without reversible embedding. In this paper we present two effective policies to reduce the gate cost and complexity for the existing direct reversible mapping methods without reversible embedding. In order to develop new cost reduction policies we consider the cost influence of Toffoli module according to NOT gate arrangement in classical circuits. From this we deduced an inverse proportional property between inverting input numbers of classical AND/OR gates and reversible Toffoli module cost based on a fact - the inverting inputs of classical AND(OR) gates increase(decrease) the Toffoli module cost. We confirm the applications of the inverting input rearrangement and maximum fan-out policies preceding direct reversible mapping will be effective method to improve the reversible Toffoli module cost and complexity with the parallel using of the fan-out and supercell ones.

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