Gate Cost Reduction Policy for Direct Irreversible-to-Reversible Mapping Method without Reversible Embedding

가역 임베딩 없는 직접적 비가역-가역회로 매핑 방법의 게이트비용 절감 방안

  • 박동영 (강릉원주대학교 정보통신공학과) ;
  • 정연만 (강릉원주대학교 정보통신공학과)
  • Received : 2014.09.11
  • Accepted : 2014.11.10
  • Published : 2014.11.30


For the last three decades after the advent of the Toffoli gate in 1980, while many reversible circuit syntheses have been presented reversible embedding methods onto suitable reversible functions, only a few proposed direct irreversible-to-reversible mapping methods without reversible embedding. In this paper we present two effective policies to reduce the gate cost and complexity for the existing direct reversible mapping methods without reversible embedding. In order to develop new cost reduction policies we consider the cost influence of Toffoli module according to NOT gate arrangement in classical circuits. From this we deduced an inverse proportional property between inverting input numbers of classical AND/OR gates and reversible Toffoli module cost based on a fact - the inverting inputs of classical AND(OR) gates increase(decrease) the Toffoli module cost. We confirm the applications of the inverting input rearrangement and maximum fan-out policies preceding direct reversible mapping will be effective method to improve the reversible Toffoli module cost and complexity with the parallel using of the fan-out and supercell ones.


  1. D. Maslov and G. W. Dueck, "Reversible Cascades with Minimal Garbage," IEEE Trans. CAD, vol. 23, no. 11, 2004, pp. 1497-1509.
  2. R. Wille and R. Dreschler, "BDD-based Synthesis of Reversible Logic Circuits for Larger Functions," Proc. DAC, San Francisco, CA, July 26-31, 2009, pp. 270-275.
  3. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Synthesis of Reversible Logic Circuits," IEEE Trans. CAD, vol. 22, no. 6, 2003, pp. 710-722.
  4. D. Michael Miller, Robert Wille, and Gerhard W. Dueck, "Synthesizing Reversible Circuits for Irreversible Functions," 12th Euromicro Conf. on Digital System Design/Architectures, Methods and Tools, Patras, Greece, Aug. 2009, pp. 749-756.
  5. D.-Y. Park and Y.-M. Jeong, "A New Functional Synthesis Method for Macro Quantum Circuits Realized in Affine-Controlled NCV-Gates," J. of the Korea Institute of Electronic Communication Science, vol. 9, no. 4, 2014, pp. 447-454.
  6. Z. Zilic, K. Radecka, and A. Khazamiphur, "Reversible circuit technology mapping from non-reversible specifications," Proc. Design Automation and Test in Europe, Nice, France, Apr. 2007, pp. 558-563.
  7. S. Sultana and K. Radecka, "Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network," IEEE 42th Int. Symp. on Multiple-Valued Logic, Victoria, Canada, May 2011. pp. 147-152.