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Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries

  • Pandian, M. Karthigai ;
  • Balamurugan, N.B.
  • Received : 2013.08.29
  • Accepted : 2014.07.17
  • Published : 2014.11.01

Abstract

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

Keywords

Junction Based Cylindrical Surrounding Gate (JBCSG) silicon nanowire transistor;Rectangular surrounding gate silicon nanowire transistor;Threshold voltage;Parabolic approximation;silicon thickness;Channel Length;drain Bias

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