Instruction-level Power Model for Asynchronous Processor

명령어 레벨의 비동기식 프로세서 소비 전력 모델

  • Lee, Je-Hoon (Division of Electronics and Information Communication Eng., Samcheok Campus, Kangwon National University)
  • 이제훈 (강원대학교 삼척캠퍼스 전자정보통신공학부)
  • Received : 2012.04.09
  • Accepted : 2012.07.12
  • Published : 2012.07.31


This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.


Supported by : 한국연구재단


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