Design of CMOS Op Amps Using Adaptive Modeling of Transistor Parameters

  • Yu, Sang-Dae (School of Electronics Engineering, Kyungpook National University)
  • Received : 2011.07.25
  • Published : 2012.03.31


A design paradigm using sequential geometric programming is presented to accurately design CMOS op amps with BSIM3. It is based on new adaptive modeling of transistor parameters through the operating point simulation. This has low modeling cost as well as great simplicity and high accuracy. The short-channel dc, high-frequency small-signal, and short-channel noise models are used to characterize the physical behavior of submicron devices. For low-power and low-voltage design, this paradigm is extended to op amps operating in the subthreshold region. Since the biasing and modeling errors are less than 0.25%, the characteristics of the op amps well match simulation results. In addition, small dependency of design results on initial values indicates that a designed op amp may be close to the global optimum. Finally, the design paradigm is illustrated by optimizing CMOS op amps with accurate transfer function.



  1. G. G. E. Gielen, "CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip," IEE Proc. Comput. Digit. Tech., Vol.152, pp.317-332, May, 2005.
  2. M. M. Hershenson, S. P. Boyd, and T. H. Lee, "Optimal design of a CMOS op amp via geometric programming," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.20, pp.1-21, Jan., 2001.
  3. P. Mandal and V. Visvanathan, "CMOS op-amp sizing using a geometric programming formulation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.20, pp.22-38, Jan., 2001.
  4. X. Li, P. Gopalakrishnan, Y. Xu, and L. T. Pileggi, "Robust analog/RF circuit design with projectionbased performance modeling," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.26, pp.2-15, Jan., 2007.
  5. W. Daems, G. Gielen, and W. Sansen, "Simulationbased generation of posynomial performance models for the sizing of analog integrated circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.22, pp.517-534, May, 2003.
  6. J. Kim, J. Lee, L. Vandenberghe, and C.K. K. Yang, "Techniques for improving the accuracy of geometric-programming based analog circuit design optimization," in Proc. IEEE Int. Conf. Computer-Aided Design, 2004, pp.863-870.
  7. J. Kim, L. Vandenberghe, and C.K. K. Yang, "Convex piecewise-linear modeling method for circuit optimization via geometric programming," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.29, pp.1823-1827, Nov., 2010.
  8. W. Gao and R. Hornsey "A power optimization method for CMOS op amps using sub-space based geometric programming," in Design, Automation and Test in Europe, 2010, pp.508-513.
  9. V. Aggarwal and U.M. O'Reilly, "Simulationbased reusable posynomial models for MOS transistor parameters," in Design, Automation and Test in Europe, 2007, pp.69-74.
  10. S. DasGupta and P. Mandal, "An improvised MOS transistor model suitable for geometric program based analog circuit sizing in sub-micron technology," in Proc. IEEE VLSI Design, 2010, pp.294-299.
  11. M.H. Maghami, F. Inanlou, and R. Lotfi, "Simulation-equation-based methodology for design of CMOS amplifiers using geometric programming," in Proc. IEEE Electron., Circuits and Syst., 2008, pp.360-363.
  12. J. Jeon, B. G. Park, and H. Shin, "Investigation of thermal noise factor in nanoscale MOSFETs," Journal of Semiconductor Technology and Science, Vol.10, pp.225-231, Sep., 2010.
  13. R. J. Duffin, E. L. Peterson, and C. Zener, Geometric Programming-Theory and Application. New York: Wiley, 1967.
  14. K. O. Kortanek, X. Xu, and Y. Ye, "An infeasible interior-point algorithm for solving primal and dual geometric progams," Math. Programming, Vol.76, pp.155-181, 1996.
  15. A. Mutapcic, K. Koh, S. Kim, and S. Boyd, "ggplab: A Matlab toolbox for geometric programming,"˜boyd/ggplab, Version 1.0, May, 2006.
  16. N. Arora, MOSFET Models for VLSI Circuit Simulation. Springer-Verlag, 1993.
  17. W. Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4. John Wiley & Sons, 2001.
  18. E. A. Vittoz, "Weak inversion for ultra low-power and very low-voltage circuits," in Proc. IEEE Asian Solid-State Circuits Conference, Nov., 2009, pp.129-132.
  19. C. C. Enz and E. A. Vittoz, Charge-based MOS Transistor Modeling. John Wiley & Sons, 2006.
  20. D. M. Binkley, Tradeoffs and Optimization in Analog CMOS Design. John Wiley & Sons, 2008.
  21. M. J. Deen, C. H. Chen, S. Asgaran, A. Rezvani, J. Tao, and Y. Kiyota, "High-frequency noise of modern MOSFETs," IEEE Trans. Electron. Devices, Vol.53, pp.2062-2081, Sep., 2006.
  22. M. Chiang, C. W. Tan, D. P. Palomar, D. O'Neill, and D. Julian, "Power control by geometric programming," IEEE Trans. Wireless Communications, Vol.6, pp.2640-2651, Jul., 2007.
  23. B. Y. Kamath, R. G. Meyer, and P. R. Gray, "Relationship between frequency response and settling time of operational amplifiers," IEEE J. Solid-State Circuits, Vol.9, pp.347-352, Dec., 1974.
  24. D. J. Comer and D. T. Comer, "Using the weak inversion region to optimize input stage design of CMOS op amps," IEEE Trans. Circuits and Systems II, Vol.51, pp.8-14, Jan., 2004.
  25. S. M. Mallya and J. H. Nevin, "Design procedures for a fully differential folded-cascode CMOS operational amplifier," IEEE J. Solid-State Circuits, Vol.24, pp.1737-1740, Dec., 1989.

Cited by

  1. A Unified Channel Thermal Noise Model for Short Channel MOS Transistors vol.13, pp.3, 2013,
  2. Small-Signal Analysis of a Differential Two-Stage Folded-Cascode CMOS Op Amp vol.14, pp.6, 2014,
  3. Design Optimization of CML-Based High-Speed Digital Circuits vol.51, pp.11, 2014,
  4. Modeling and sizing of non-linear CMOS analog circuits used in mixed signal systems pp.1573-1979, 2019,