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Low Temperature Sintering and Electrical Properties of Bi-based ZnO Chip Varistor

Bi계 ZnO 칩 바리스터의 저온소결과 전기적 특성

  • Hong, Youn-Woo (Future Convergence Ceramic Division, Korea Institute of Ceramic Engineering and Technology) ;
  • Shin, Hyo-Soon (Future Convergence Ceramic Division, Korea Institute of Ceramic Engineering and Technology) ;
  • Yeo, Dong-Hun (Future Convergence Ceramic Division, Korea Institute of Ceramic Engineering and Technology) ;
  • Kim, Jin-Ho (School of Materials Science and Engineering, Kyungpook National University)
  • 홍연우 (한국세라믹기술원 미래융합세라믹본부) ;
  • 신효순 (한국세라믹기술원 미래융합세라믹본부) ;
  • 여동훈 (한국세라믹기술원 미래융합세라믹본부) ;
  • 김진호 (경북대학교 신소재공학부)
  • Received : 2011.10.06
  • Accepted : 2011.10.24
  • Published : 2011.11.01

Abstract

The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850~900$^{\circ}C$ for 1 h in air. A good varistor characteristics ($V_n$= 9.3~15.4 V, a= 23~24, $I_L$= 1.0~1.6 ${\mu}A$) were revealed but formed $Zn_i^{{\cdot}{\cdot}}$(0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.

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