Low Complexity Channel Preprocessor for Multiple Antenna Communication Systems

다중 안테나 통신 시스템을 위한 저복잡도 채널 전처리 프로세서

  • Hwang, You-Sun (School of Electronics, Telecommunication and Computer Eng., Korea Aerospace University) ;
  • Jang, Soo-Hyun (School of Electronics, Telecommunication and Computer Eng., Korea Aerospace University) ;
  • Han, Chul-Hee (Samsung Thales, Co. Ltd.) ;
  • Choi, Sung-Nam (Samsung Thales, Co. Ltd.) ;
  • Jung, Yun-Ho (School of Electronics, Telecommunication and Computer Eng., Korea Aerospace University)
  • 황유선 (한국항공대학교 항공전자 및 정보통신 공학부) ;
  • 장수현 (한국항공대학교 항공전자 및 정보통신 공학부) ;
  • 한철희 (삼성탈레스(주)) ;
  • 최성남 (삼성탈레스(주)) ;
  • 정윤호 (한국항공대학교 항공전자 및 정보통신 공학부)
  • Received : 2011.02.18
  • Accepted : 2011.04.30
  • Published : 2011.04.30


In this paper, the channel preprocessor with an area-efficient architecture is proposed for the MIMO symbol detector which can support four transmit and receive antennas. The proposed channel preprocessor can shrink the channel dimension to reduce the hardware complexity of the MIMO symbol detector. Also, the proposed channel preprocessor is implemented with very low complexity by using QR decomposition (QRD) and log-number system (LNS). By applying QRD and LNS to the nulling matrix calculation block, the numbers of matrix-multiplications and matrix-divisions are decreased and thus the complexity of the proposed channel preprocessor is significantly reduced. The proposed channel preprocessor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. With the proposed channel preprocessor, the number of logic gates for channel preprocessor is reduced by 20.2% compared with the conventional architecture.


Supported by : 한국연구재단


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