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Compact Design of the Advanced Encryption Standard Algorithm for IEEE 802.15.4 Devices

  • Song, Oh-Young (School of Electrical and Electronic Engineering, Chung-Ang University) ;
  • Kim, Ji-Ho (School of Electrical and Electronic Engineering, Chung-Ang University)
  • Received : 2010.08.16
  • Accepted : 2010.12.30
  • Published : 2011.05.02

Abstract

For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.

References

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  2. Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box vol.25, pp.05, 2016, https://doi.org/10.1142/S0218126616500377