Optimized DES Core Implementation for Commercial FPGA Cluster System

상용 FPGA 클러스터 시스템 기반의 최적화된 DES 코어 설계

  • Received : 2011.01.18
  • Accepted : 2011.04.04
  • Published : 2011.04.30

Abstract

The previous FPGA cluster systems for a brute force search of DES keyspace have showed cost efficient performance, but the research on optimized implementation of the DES algorithm on a single FPGA has been insufficient. In this paper, the optimized DES implementation for a single FPGA of the commercial FPGA cluster system with 77 Xilinx Virtex5-LX50 FPGAs is proposed. Design space exploration using the number of pipeline stages in a DES core, the number of DES cores and the maximum clock frequency of a DES core is performed which leads to integrating 16 DES cores running at 333MHz. Also low power design is applied to reduce the loss of performance caused by limitation of power supply on each FPGA which results in fitting 8 DES cores running at 333MHz. When the proposed DES implementations would be used in the FPGA cluster system, it is estimated that the DES key would be found at most 2.03 days and 4.06 days respectively.

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