GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections

  • Pak, Jun-So (Dept. of Electrical Engineering, KAIST) ;
  • Cho, Jong-Hyun (Dept. of Electrical Engineering, KAIST) ;
  • Kim, Joo-Hee (Dept. of Electrical Engineering, KAIST) ;
  • Kim, Ki-Young (Dept. of Electrical Engineering, KAIST) ;
  • Kim, Hee-Gon (Dept. of Electrical Engineering, KAIST) ;
  • Lee, Jun-Ho (Advanced Design Team, Hynix Semiconductor Inc.) ;
  • Lee, Hyung-Dong (Advanced Design Team, Hynix Semiconductor Inc.) ;
  • Park, Kun-Woo (Advanced Design Team, Hynix Semiconductor Inc.) ;
  • Kim, Joung-Ho (Dept. of Electrical Engineering, KAIST)
  • Received : 2011.05.16
  • Published : 2011.12.31


GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.


GHz EMI;3D;Chip-PDN;3D IC;TSV;Stacking Configuration


Grant : Wafer Level 3D IC Design and Integration, Core Process Development of the 3D Integration for System IC

Supported by : KEIT


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