Analysis of the Single Event Effect of the Science Technology Satellite-3 On-Board Computer under Proton Irradiation

과학기술위성 3호 온보드 컴퓨터의 양성자 빔에 의한 Single Event Effect 분석

  • 강동수 (충남대학교 컴퓨터공학과 대학원) ;
  • 오대수 (한국과학기술원 인공위성센터) ;
  • 고대호 (한국항공우주연구원) ;
  • 백종철 (AP 시스템(주)) ;
  • 김형신 (충남대학교 컴퓨터공학과) ;
  • 장경선 (충남대학교 컴퓨터공학과)
  • Received : 2011.07.12
  • Accepted : 2011.11.22
  • Published : 2011.12.01


Field Programmable Gate Array(FPGA)s are replacing traditional integrated circuits for space applications due to their lower development cost as well as reconfigurability. However, they are very sensitive to single event upset (SEU) caused by space radiation environment. In order to mitigate the SEU, on-board computer of STSAT-3 employed a triple modular redundancy(TMR) and scrubbing scheme. Experimental results showed that upset threshold energy was improved from 10.6 MeV to 20.3 MeV when the TMR and the scrubbing were applied to the on-board computer. Combining the experimental results with the orbit simulation results, calculated bit-flip rate of on-board computer is 1.23 bit-flips/day assuming in the worst case of STSAT-3 orbit.


Supported by : National Research Foundation of Korea(NRF)


  1. Neil W. Bergmann and Anwar S. Dawood, "Reconfigurable Computers in Space: Problems, Solutions and Future Directions", the Proc. of Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999.
  2. Bolchini C., Miele A., Santambrogio M. D., "TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs", the Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, IEEE, 2007, pp.87-95.
  3. Barth J., "Radiation Environment", IEEE NSREC Short Course, July, 1997.
  4. Normand E., "Single Event Upset at Ground Level", IEEE Transaction on Nuclear Science, Vol.43, No.6, Dec. 1996, pp.2742-2750.
  5. Lima F., Carro L., Reis R., "Designing Fault Toleant Systems into SRAM-based FPGAs", the Proc. of Design Automation Conference'03, IEEE/ACM, 2003, pp.650-655.
  6. Xilinx Inc., Virtex-4 User Guide, 2007.
  7. Actel Inc., RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Data Sheet, 2010.
  8. Aeroflex Giasler Inc., GRLIB IP Core User's Manual, 2009.
  9. E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, and J. Fabula, "Radiation testing update, SEU mitigation, and availability analysis of the Virtex FPGA for space re-configurable computing", the Proc. of MAPLD '00, 2000.
  10. C. Carmichael, Xilinx Application Note 197. 2006.
  11. F. Lima, L. Sterpone, L. Carro, M. Sonza Reorda, "On the Optimal Deisgn of Triple Modulear Redundancy Logic for SRAM-based FPGAs", the Proc. of Deisgn Automation and Test in Europe (DATE)'05, 2005, pp.1290-1295.
  12. B. Pratt, M. Caffrey, P. Graham, K. Morgan, M. Wirthlin, "Improving FPGA Design Robustness with Partial TMR", the Proc. of Annual International Reliability Physics Symposium, 2006, pp.226-233.
  13. P. K. Samudrala, J. Ramos, and S. Katkoori, "Selective Triple Modular Redundancy (STMR) Based Single-Event Upset (SEU) Tolerant Synthesis for FPGAs", IEEE Transaction on Nuclear Science, Vol.51, No.5, 2004, pp.2957-2970.
  14. Xiaoxuan She, P. K. Samudrals, "Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation", the Proc. of NASA/ESA Conference on Adaptive Hardware and Systems, 2009, pp.344-350.
  15. KIRAMS Hompage,
  16. Dong-Kang, Dae-Soo Oh, Kyoung-Son Jhang, "Design and Implemenation of a Radiation Tolerant On-Board Computer for Science Technology Satellite-3", the Proc. of NASA/ESA Conference on Adaptive Hardware and Systems, 2010, pp.17-23.
  17. 고대호, 이승헌, 이성세, 박종오, 심은섭, "Virtex-5 XC5VLX50 Field Programming Gate Array를 이용한 양성자 빔에서의 단일 현상 효과 특성 분석", 한국물리학회지 "새물리", Vol.59, No.6, 2009, pp.450-454.
  18. STSAT-3 System Ciritical Design Review, 2009.
  19. J. I. Vette, "The NASA/National Space Science Data Center Trapped Radiation Environment Model Program (1964-1991)", NSSDC 91-29, NASA/Goddard Space Flight Center, National Space Science Data Center, Greenbelt, MD, 1991.