Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Analysis of the Threshold Voltage Instability of Bottom-Gated ZnO TFTs with Low-Frequency Noise Measurements

Low-Frequency Noise 측정을 통한 Bottom-Gated ZnO TFT의 문턱전압 불안정성 연구

  • Jeong, Kwang-Seok (Department of Electronic Engineering, Chungnam National University) ;
  • Kim, Young-Su (Department of Electronic Engineering, Chungnam National University) ;
  • Park, Jeong-Gyu (Department of Electronic Engineering, Chungnam National University) ;
  • Yang, Seung-Dong (Department of Electronic Engineering, Chungnam National University) ;
  • Kim, Yu-Mi (Department of Electronic Engineering, Chungnam National University) ;
  • Yun, Ho-Jin (Department of Electronic Engineering, Chungnam National University) ;
  • Han, In-Shik (Department of Electronic Engineering, Chungnam National University) ;
  • Lee, Hi-Deok (Department of Electronic Engineering, Chungnam National University) ;
  • Lee, Ga-Won (Department of Electronic Engineering, Chungnam National University)
  • Received : 2010.05.17
  • Accepted : 2010.06.04
  • Published : 2010.07.01

Abstract

Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

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Acknowledgement

Supported by : 한국연구재단

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