A hardware design of Rate control algorithm for H.264

H.264 율제어 알고리듬의 하드웨어 설계

  • Suh, Ki-Bum (Division of Railway electical & information Communication Engineering, Woosong University)
  • 서기범 (우송대학교 철도전기정보통신학부)
  • Published : 2010.01.31


In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.


H.264;Rate control;Floating point unit


  1. ISO/IEC 14496-10.2005 International Standard.
  2. JVT-G012(Document from JVT(
  3. Chang-hyun Lee, Seong-joo Lee, Yun-je Oh, Jaeseok Kim,"Cost-Effective Frame-Layer H.264 Rate Control for Low Bit Rate Video," icme, pp.697-700, 2006 IEEE International Conference on Multimedia and Expo, 2006
  4. 손남례, 신윤정, 이귀상,"장면전환에 효율적인 H.264/AVC 비트율제어 기법", 대한전자공회 논문지,제 44권 SP편 제1호,pp 26-39. 2007.1
  5. Loren Merritt and Rahul Vanam," Improved rate control and Motion Estimation for H.264 Encoder", ICIP 2007, pp V-309-312, 2007.6
  6. H.264/AVC encoder reference software 13.2 (available
  7. 이일주,임성준, 채현석,"H.264 코덱을 사용한 고성능 DVR 시스템 개발에 관한 연구", 한국산학기술학회논문지, Vol 10. No.1, pp 110-116,2009.1
  8. 정준모,."ARM-Excalibur를 이용한 H.264/AVC 디코더 의 HW/SW 병행설계", 한국 산학기술학회 논문지, Vol.10, No.7, pp1480-1483,2009.10
  9. IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic. 1985