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A hardware design of Rate control algorithm for H.264

H.264 율제어 알고리듬의 하드웨어 설계

  • Suh, Ki-Bum (Division of Railway electical & information Communication Engineering, Woosong University)
  • 서기범 (우송대학교 철도전기정보통신학부)
  • Published : 2010.01.31

Abstract

In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.

Keywords

H.264;Rate control;Floating point unit

References

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