A Simulation Study on the Structural Optimization of a 800 V 4H-SiC Power DMOSFET

800 V급 4H-SiC DMOSFET 전력 소자 구조 최적화 시뮬레이션

  • 최창용 (광운대학교 전자재료공학과) ;
  • 강민석 (광운대학교 전자재료공학과) ;
  • 방욱 (한국전기연구원 에너지반도체 연구센터) ;
  • 김상철 (한국전기연구원 에너지반도체 연구센터) ;
  • 김남균 (한국전기연구원 에너지반도체 연구센터) ;
  • 구상모 (광운대학교 전자재료공학과)
  • Published : 2009.08.01


In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.


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