Improved Electrical Characteristics of Symmetrical Tunneling Dielectrics Stacked with SiO2 and Si3N4 Layers by Annealing Processes for Non-volatile Memory Applications

비휘발성 메모리를 위한 SiO2와 Si3N4가 대칭적으로 적층된 터널링 절연막의 전기적 특성과 열처리를 통한 특성 개선효과

  • 김민수 (광운대학교 전자재료공학과) ;
  • 정명호 (광운대학교 전자재료공학과) ;
  • 김관수 (광운대학교 전자재료공학과) ;
  • 박군호 (광운대학교 전자재료공학과) ;
  • 정종완 (세종대학교 나노신소재공학부) ;
  • 정홍배 (광운대학교 전자재료공학과) ;
  • 이영희 (광운대학교 전자재료공학과) ;
  • 조원주 (광운대학교 전자재료공학과)
  • Published : 2009.05.01


The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.


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