- Volume 9 Issue 4
DOI QR Code
High Performance Data Cache Memory Architecture
고성능 데이터 캐시 메모리 구조
- Kim, Hong-Sik (Dept. of Electrical & Electronic Engineering, Yonsei University) ;
- Kim, Cheong-Ghil (Dept. of Computer Science, Namseoul University)
- Published : 2008.08.31
In this paper, a new high performance data cache scheme that improves exploitation of both the spatial and temporal locality is proposed. The proposed data cache consists of a hardware prefetch unit and two sub-caches such as a direct-mapped (DM) cache with a large block size and a fully associative buffer with a small block size. Spatial locality is exploited by fetching and storing large blocks into a direct mapped cache, and is enhanced by prefetching a neighboring block when a DM cache hit occurs. Temporal locality is exploited by storing small blocks from the DM cache in the fully associative buffer according to their activity in the DM cache when they are replaced. Experimental results on Spec2000 programs show that the proposed scheme can reduce the average miss ratio by
data cache;temporal locality;spatial locality;and prefetch;AMAT(average memory access time)
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