Power-aware Test Framework for NoC(Network-on-Chip)

NoC에서의 저전력 테스트 구조

  • Published : 2007.06.30

Abstract

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

Keywords

Test;Network-on-Chip;TAM;Low-power