Low Power Testing in NoC(Network-on-Chip) using test pattern reconfiguration

테스트 패턴 재구성을 이용한 NoC(Network-on-Chip)의 저전력 테스트

  • 정준모 (군산대학교 전자정보공학부)
  • Published : 2007.04.30

Abstract

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

Keywords

test;NoC(Network-on chip);dft;scan chain;test pattern