A Low Power FPGA Architecture using Three-dimensional Structure

3차원 구조를 이용한 저전력 FPGA 구조

  • 김판기 (연세대학교 프로세서연구실) ;
  • 이형표 (연세대학교 프로세서연구실) ;
  • 김현필 (연세대학교 프로세서연구실) ;
  • 전호윤 (연세대학교 프로세서연구실) ;
  • 이용석 (연세대학교 프로세서연구실)
  • Published : 2007.12.15

Abstract

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

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