A Low Power Multi Level Oscillator Fabricated in $0.35{\mu}m$ Standard CMOS Process

$0.35{\mu}m$ 표준 CMOS 공정에서 제작된 저전력 다중 발진기

  • 채용웅 (계명대 공대 전자공학과) ;
  • 윤광열 (계명대 공대 전자공학과)
  • Published : 2006.08.01


An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.


Multi Level Oscillator;Analog Memory;PLL;VCO


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