A Low Power Multi Level Oscillator Fabricated in $0.35{\mu}m$ Standard CMOS Process

$0.35{\mu}m$ 표준 CMOS 공정에서 제작된 저전력 다중 발진기

  • 채용웅 (계명대 공대 전자공학과) ;
  • 윤광열 (계명대 공대 전자공학과)
  • Published : 2006.08.01

Abstract

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

Keywords

Multi Level Oscillator;Analog Memory;PLL;VCO

References

  1. R. Harrison, P. Hasler,B. A. Minch, 'Floating-Gate CMOS Analog Memory Cell Array,' in Proc. Int. Symp. Circuits and Systems, Monterey, CA, 1998 https://doi.org/10.1109/ISCAS.1998.706877
  2. R. Harrison, A. Bragg, and P. Hasler, 'A CMOS Programmable Analog Memory-Cell Array Using Floating-Gate Circuits,' IEEE Trans. on circuits and systems, Vol. 48, No.1, pp. 4-11, Jan. 2001 https://doi.org/10.1109/82.913181
  3. Y. Y. Chai, 'A $2{\times}2$ Analog Memory Implemented with a Special Layout Injector,' IEEE Journal of Solid-State Circuits, Vol. 32, pp.856-859, June 1996 https://doi.org/10.1109/4.509874
  4. 채용웅, 정동진, '0.35um 싱글폴리 표준 CMOS공정에서 제작된 아날로그 메모리 셀의 프로그래밍 특성', 전기학회논문지, VOL.53D, NO.6, pp.425-432, June 2004
  5. W. D. Brown and J. E. Brewer, 'Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices,' IEEE New York, pp.6-9, 1998
  6. K. Ohsaki, N. Asarnoto, and S. Takagaki, 'A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,' IEEE J. Solid State circuit, Vol. 29, No.3, pp, 311-316, Mar. 1994 https://doi.org/10.1109/4.278354
  7. D. H. Wolaver, 'Phase-Locked Loop Circuit Design', Prentice Hall, New Jersey, pp.9-106, 1991
  8. 이승훈, 김범섭, 송민규, 최중호, CMOS 아날로그/혼성모드 집적시스템 설계(下). 시그마프레스, pp.257-304, 1999