An FPGA Implementation of Parallel Hardware Architecture for the Real-time Window-based Image Processing

실시간 윈도우 기반 영상 처리를 위한 병렬 하드웨어 구조의 FPGA 구현

  • 진승훈 (성균관대학교 전기전자공학과) ;
  • 조정욱 (성균관대학교 정보통신공학부) ;
  • 권기호 (성균관대학교 정보통신공학부) ;
  • 전재욱 (성균관대학교 정보통신공학부)
  • Published : 2006.06.01


A window-based image processing is an elementary part of image processing area. Because window-based image processing is computationally intensive and data intensive, it is hard to perform ail of the operations of a window-based image processing in real-time by using a software program on general-purpose computers. This paper proposes a parallel hardware architecture that can perform a window-based image processing in real-time using FPGA(Field Programmable Gate Array). A dynamic threshold circuit and a local histogram equalization circuit of the proposed architecture are designed using VHDL(VHSIC Hardware Description Language) and implemented with an FPGA. The performances of both implementations are measured.


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