Optimization of Capacitor Threshold VT Implantation for Planar P-MOS DRAM Cell

평면구조 P-MOS DRAM 셀의 커패시터 VT 이온주입의 최적화

  • 장성근 (청운대학교 디지털방송공학과) ;
  • 김윤장 (매그나칩 반도체 DSD소자 2팀)
  • Published : 2006.02.01


We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.


  1. M. Inohara, I. Tamura, T. Yamaguchi, H. Koike, Y. Enomoto, S. Arakawa, T. Watanabe, E. Ide, S. Kadomura, and K. Sunouchi, 'High Performance Copper and Low-k Interconnect Technology Fully Compatible to 90 nm-node SOC application(CMOS4)', IEDM Tech. Digest, p. 79, 2002
  2. T. Yamada, K. Takahashi, H. Oyamatsu, H. Nagano, T. Sato, I. Mizushima, S. Nitta, T. Hojo, K. Kokubun, K. Yasumoto, Y. Matsubara, T. Yoshida, S. Yamada, Y. Tsunashima, Y. Saito, S. Nadahara, Y. Katsumata, M. Yoshimi, and H. Ishiuchi, 'An Embedded DRAM Technology on SOI/Nulk Hybrid Substrate Formed with SEG Process for High-End SOC Application', VLSI Tech. Digest, p. 112, 2002
  3. W. Leung, F. Chieh, and M. Jones, ' The Ideal SOC Memory IT-SRAM'', ASIC/SOC Conference, Proceeding, p, 13, 2000
  4. AL F. Tasch, R. C. Frye, and H. S. Fu, ' The charge-coupled RAM cell concept', IEEE Journal of Solid State Circuits, Vol. Sc-11, No.1, p. 58. 1976
  5. AL F. Tasch, H. S. Fu, T. C. Holloway, and R. C. Frye, 'Charge capacity analysis of the charge-coupled RAM cell', IEEE Journal of Solid State circuits, Vol. Sc-11, No. 5, p, 575, 1976
  6. T. Hamamoto, S. Sugiura, and S. Sawada, 'On the retention time distribution of dynamic random access memory (DRAM) ', IEEE Tran., on Electron Devices, Vol. 45, No. 6, p. 1300, 1998
  7. H. Kujirai, K. Ohyu, M. Moniwa, H. Kato, K. Nakai, H. Iwai, M. Nanba, and A. Ogishima, 'Data Retention Time in DRAM with WSix/P+poly-Si Gate NMOS Cell Transistors', IEDM Tech. Digest, p. 395, 2001
  8. S. Ueno, T. Yamashita, H. Oda, S. Komori, Y. Inoue, and T. Nishimura, 'Leakage Current Observation on Irregular Local PN Junctions Forming the Tail Distribution of DRAM Retention Characteristics, with New Test Structure', IEDM Tech. Digest, p. 153, 1998