A Study on the Formation of Trench Gate for High Power DMOSFET Applications

고 전력 DMOSFET 응용을 위한 트렌치 게이트 형성에 관한 연구

  • 박훈수 (위덕대학교 반도체전자공학부) ;
  • 구진근 (한국전자통신연구원 다기능소자) ;
  • 이영기 (위덕대학교 반도체전자공학부)
  • Published : 2004.07.01


In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.


  1. IEEE Transaction on Electron Devices v.ED-49 no.8 A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact N.Fujishima;A.Sugi;S.Kajiwara;K.Matsubara;Y.Nagayama;C.Salama
  2. 전기전자재료학회논문지 v.15 no.3 고내압 특성을 위한 진성영역과 트렌치 구조를 갖는 베이스 저항 사이리스터 강이구;성만영
  3. Proceeding of ISPSD A new concept for the lateral DMOS transistors for smart power ICs M.Zitouni;F.Morancho;P.Rossel;H.Tranduc;I.Pages
  4. IEEE Transaction on Electron Devices v.ED-34 no.7 An ultra-low on-resistance power MOSFET fabricated by using a fully self-aligned process D.Ueda;H.Takagi;G.Kano
  5. 전기전자재료학회논문지 v.13 no.5 레치업 특성의 개선과 고속 스위칭 특성을 위한 다중 게이트 구조의 새로운 LIGBT 강이구;성만영
  6. Proceeding of IEDM A 1 million-cell 2.0 mΩ, 30V Trench FET utilizing 32 Mcell/in2 density with distributed voltage clamping R.K.Williams;W,Grabowski;M.Darwish;M.Chang;H.Yilmaz;K.Owyang
  7. Proceeding of SSDM 25V-13 mΩ-mm2 low on-resistance novel structure trench gate LDMOS Y,Kawaguchi;T.Sano;A.Nakagawa
  8. 전기전자재료학회논문지 v.14 no.7 스마트 파워 IC를 위한 P+ driver 구조의 횡형 트렌치 IGBT 문승현;강이구;성만영;김상식