- Volume 12 Issue 2
This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named
- Proc. of IEEE Workshop on VLSI Signal Processing Compiled simulation of programmable DSP Architectures V.Zivojnovic;S.Tjiang;H.Meyr
- Proc. of the Design Automation Conference(DAC) Generation of softweare tools from porcessor descriptions for hardware/software codesign M.Hartoog;J.Rowson;et al.
- Proc. Int. Conf. on Signal Processing Application and Technology Fast Simulation of the TITMS 320C54x DSP S.Pees;V.Zivojnovic;A.Ropers;H.Meyr
- Proceedings of European Design and Test Conference, Paris France Describing instruction set processors using nML A.Fauth;J.VanPraet;M.Freericks
- Proc. of the Conference on Design, Automation & Test in Europe EXPRESSION:A language for architecture expoloration through compiler/simulator retargetability A.Halambi;P.Grun;et al.
- Proc. DAC ISDL:An insturction set description language for retargetability G.Hadjiyiannis et al.
- Proceedings of the IEEE Workshop on VLSI Signal Processing LISA-machine description language and generic machine model for HW/SW co-design V.Zivojnovic;S.Pees;H.Meyr
- Proc. of the Asia & South Pacific Design Automation Conference(ASP-DAC0 Generation of Interpretive and Compild Instruction Set Simulators R.Leupers;J.Elste;B.Landwehr
- Proc. IEEE/ACM International Symposium on MediaBench:a tool for evaluating and synthesizing multimedia and communications systems C.Lee;M.Portkonjak;W.H.Mangione-Smith