Performance Improvement of ASIP Assembly Simulator Using Compiled Simulation Technique

컴파일방식 시뮬레이션 기법을 이용한 ASIP 어셈블리 시뮬레이터의 성능 향상

  • 김호영 (한국과학기술원 전자전산학과) ;
  • 김탁곤 (한국과학기술원 전자전산학과)
  • Published : 2003.06.01


This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.


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