Impact of Post Gate Oxidation Anneal on Negative Bias Temperature Instability of Deep Submicron PMOSFETs

게이트 산화막 어닐링을 이용한 서브 마이크론 PMOS 트랜지스터의 NBTI 향상

  • 김영민 (홍익대학교 전자전기공학부)
  • Published : 2003.03.01


Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.


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