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The Improved Electrical Endurance(Program/Erase Cycles) Characteristics of SONOS Nonvolatile Memory Device

SONOS 비휘발성 기억소자의 향상된 프로그램/소거 반복 특성

  • 김병철 (진주산업대학교 전자공학과) ;
  • 서광열 (광운대학교 반도체 및 신소재공학과)
  • Published : 2003.01.01

Abstract

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

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