Debugging Problem for Multi-Million Gates FPGAs and the Way to Solve It

초고집적 FPGA디버깅의 문제점 및 해결책

  • Yang, Se-Yang (Dept.of Electronics Electric Information Computer Engineering, Busan National University)
  • 양세양 (부산대학교 전자전기정보 컴퓨터공학부)
  • Published : 2002.04.01


As today's field programmable gate arrays have very large logic capacity as well as relatively fast operation speed, they're widely used in many application areas. However, debugging the design implemented in FPGA's is very time-consuming and painful as the internal signal probing usually requires large number of FPGA re-compilations, which take tremendously long time. In this paper, we analyze the problems in FPGA debugging and propose a new powerful debugging solution. With the proposed FPGA debugging solution, we can guarantee not only to provide 100% internal signal visibility without FPGA re-compilation for the design in FPGA's, but also to identify at least one design bug per FPGA compilation. An experimental result has clearly shown the proposed approach to FPGA debugging very powerful and practical.


  1. Virtex-II Platform FPGA Datasheet, Xilinx(
  2. Excalibur SOPC FPGA Datasheet, Altera (, 2000
  3. Certify Datasheet, Synplicity(, 2000
  4. ChipScope Datasheet, Xilinx (, 2001
  5. SignalTap Embedded Logic Analyzer Datasheet, Altera (, 2001
  6. SiliconExplorer Dasheet, Actel (, 2001
  7. 양세양, '시뮬레이션과 에뮬레이션의 결혼: 검증 위기의 새로운 희망,' 대한전자공학회 CAD및 VLSI연구회 신진박사논문발표 및 종합학술대회 발표논문집, 2000
  8. J. Babb et al., Logic Emulation with Virtual Wires, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 1997
  9. G. Ganapathy, et al, 'Hardware Emulation for Functional Verification of K5,' Proceeding of 33rd Design Automation Conference, June 1996
  10. Accelerating Functional Closure Using Solidify and Hardware Emulation, Whitepaper, Averant Inc.(
  11. N. Kim et al, 'Virtual Chip: Making Functional Models Work on Real Target Systems,' Proceedings of 35th Design Automation Conference, June 1998
  12. Seiyang Yang, 'Probing Apparatus and Probing Method Using the Same, and Mixed Emulation/Simulation Based on It, US Patent Pending, 1999
  13. ANSI/IEEE Std 1149.1-1990 Standard Test Acces Port and Boundary-Scan Architecture (included IEEE Std 1149.1a-1993, IEEE Std 1149.1b-1994), IEEE Standards, Piscataway, N.J., USA