An Analytical Model of Maximum Simultaneous Switching Noise for Ground Interconnection Networks in CMOS Systems

CMOS 그라운드 연결망에서의 최대 동시 스위칭 잡음의 해석 모형

  • Published : 2001.03.01


This paper presents an efficient and simple method for analyzine maximum simultaneous switching noise (SSN) on ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression, we use ${\alpha}$-power law MOS model and Taylor's series approximation. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that exist some output drivers not in transition.


CMOS;Switching Noise;Ground Interconnection Networks;Maximum Simultaneous Switching Noise


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