A Neural Metwork's FPGA Realization using Gate Level Structure

게이트레벨 연산구조를 사용한 신경합의 FPGA구현

  • Published : 2001.06.01

Abstract

Because of increasing number of integrated circuit, there is many tries of making chip of neural network and some chip is exit. but this is not prefer because YLSI technology can't support so large hardware. So imitation of whole system of neural network is more prefer. There is common procedure in signal processing as in the neural network and pattern recognition. That is multiplication of large amount of signal and reading LUT. This is identical with some operation of MLP, and need iterative and large amount of calculation, so if we make this part with hardware, overall system's velocity will be improved. So in this paper, we design neutral network, not neuron which can be used to many other fields. We realize this part by following separated bits addition method, and it can be appled in the real time parallel process processing.

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