A Study for the Improvement of Torn Oxide Defects in Shallow Trench Isolation-Chemical Mechanical Polishing (STI-CMP) Process

STI--CMP 공정에서 Torn oxide 결함 해결에 관한 연구

  • 서용진 (대불대학교 전기전자공학부) ;
  • 정헌상 (조선대학교 전기공학과) ;
  • 김상용 (아남반도체 FAB 사업부) ;
  • 이우선 (조선대학교 전기공학과) ;
  • 이강현 (조선대학교 전자정보통신공학부) ;
  • 장의구 (중앙대학교 전자전기제어공학부)
  • Published : 2001.01.01

Abstract

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

References

  1. Proc. VMIC Stress-Temperature Behavior of Oxide Films Used for InteMetal Dielectric Applications M. Galiano;E. Yieh;S. Robles;B. C. Nguyen
  2. Electrochemical Society Proceedings v.99 no.2 Study of Chemical Mechanical Polishing on Shallow Trench Isolation to Obtain Low Defect S. Y. Kim;M. K. Baek;C. I. Kim;E. G. Jang
  3. 전기전자재료학회 논문지 v.11 no.12 Chemical Mechanical Polishing(CMP) 공정을 이용한 Multilevel Metal 구조의 광역평탄화에 관한 연구 김상용;서용진;김태형;이우선;김창일;장의구
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  5. 전기전자 재료학회 논문지 v.12 no.2 CMP 공정에 기인하는 소자특성의 열화를 방지하기 위한 PMD 구조에 대한 연구 서용진;장의구