Effects of Electrical Stress on Polysilicon TFTs with Hydrogen Passivation

다결정 실리콘 박막 트랜지스터의 수소화에 따른 전기적 스트레스의 영향

  • 황성수 (삼화전자공업주식회사 R&D센터 연구원) ;
  • 황한욱 (명지대 전기공학과) ;
  • 김용상 (명지대 전기정보제어공학부)
  • Published : 1999.05.01


We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.


Hydrogenation;Polycrystalline Silicon;Thin-film transistor;Degradation;Defect creation;Charge trapping


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