A Study on the Abnormal Oxidation of Stacked Capacitor due to Underlayer Dependent Nitride Deposition

질화막 성장의 하지의존성에 따른 적층캐패시터의 이상산화에 관한 연구

  • 정양희 (여수수산대학 전기공학과)
  • Published : 1998.01.01

Abstract

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

References

  1. IEEE Trans. Electron Devices v.38 ONO inter-poly dielectric scaling for nonvolatile memory application S. Mori;E. Araki;Y. Kaneko
  2. IEDM Dig. Tech. papers High performance CMOS process for submicron 16Mb A. Bergemont;S. Deleonibus
  3. in Proc. 28th 1990 IEEE IRPS A model for EPROM intrinsic charge loss through ONO inter-poly dielectric K. Wu;C. S. Pan;J. J. Shaw;P. Freiberger;G. Sery
  4. Proc. 28th 1990 IEEE IRPS A model for EPROM intrinsic charge loss through ONO inter-poly dielectric K. Wu;C. S. Pan;J. J. Shaw;P. Freiberger;G. Sery
  5. IEEE Trans. Electron Devices v.37 no.1 A scaling methdology for oxide-nitride-oxide inter-poly dielectric for EPROM application C. S. Pan;K. Wu;P. Freiberger
  6. presented at the IEEE NVSMW. Vail. CO Scaled EPROM cell technology in 0.6um regime S. Mori;Y. Kaneko;N. Arai
  7. Sympo. on VLSI Tech. Dig. N. Ajika;M. Ohi;T. Arima;N. Tsubouchi
  8. IEDM 92 High quality ultra thin nitride film selectively deposition on poly silicon electrode by LPCVD with in situ HF vapor cleaning M. Yoshimaru;N. Inoue;M. Itoh;H. Kurogi;H. Tamura
  9. 한국전기전자재료학회 v.9 no.5 A study on the bottom oxide scaling for dieletric in stacked capacitor using L/L vacuum system Y. H. Joung;M. K. Kim
  10. IEDM Tech. Dig. M. Yoshimaru;J. Miyano;A. Sakamoto;M. Ino