Design and Implementation of 40 Gb/s Clock Recovery Module Using a Phase-Locked Loop with hold function

유지 기능을 가지는 위상고정 루프를 이용한 40 Gb/s 클락 복원 모듈 설계 및 구현

  • Park, Hyun (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
  • Woo, Dong-Sik (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
  • Kim, Jin-Joog (Satreci) ;
  • Lim, Sang-Kyu (Electronics and Telecommunications Research Institute(ETRI)) ;
  • Kim, Kang-Wook (School of Electrical Engineering and Computer Science, Kyungpook National University)
  • 박현 (경북대학교 전자전기컴퓨터학부) ;
  • 우동식 (경북대학교 전자전기컴퓨터학부) ;
  • 김진중 (세트렉아이) ;
  • 임상규 (한국전자통신연구원) ;
  • 김강욱 (경북대학교 전자전기컴퓨터학부)
  • Published : 2005.11.05

Abstract

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

Keywords

Clock and Data Recovery(CDR);40 Gb/s;Phase-Locked Loop(PLL);Hold circuit