Design and Fabrication of Synchronous Clock Recovery Module for S-DMB GaP Filler

위성 DMB 중계기의 동기용 클럭 재생 모듈 설계 및 제작

  • Chang, Lae-Kyu (Dept. of Radio Science & Engineering, Chungnam National University) ;
  • Park, Eun-Hee (Dept. of Radio Science & Engineering, Chungnam National University) ;
  • Lee, Hang-Soo (Dept. of Radio Science & Engineering, Chungnam National University) ;
  • Hong, Sung-Yong (Dept. of Radio Science & Engineering, Chungnam National University) ;
  • Park, Jung-Seo (SIGNAL TECH.)
  • 장래규 (충남대학교 전파공학과) ;
  • 박언희 (충남대학교 전파공학과) ;
  • 이행수 (충남대학교 전파공학과) ;
  • 홍성용 (충남대학교 전파공학과) ;
  • Published : 2005.11.05

Abstract

This paper describes the design and fabrication of synchronous clock recovery module for S-DMB Gap Filler. Using the 2.304MHz TTL signal from gap filler tuner, clock recovery module with 10MHz output frequency including holdover function is designed. The measured performance of the clock recovery module shows a stability of less than 0.01ppm, 29 sec stability time, 10 sec holdover time, and maximum -113dBc/Hz@100Hz phase noise.

Keywords

S-DMB;Gap Filler;Clock Recovery module;Holdover;PLL