Fine-Grain Pipeline Control Circuit for High Performance Microprocessors

고성능 마이크로프로세서를 위한 파이프라인 제어로직

  • 배상태 (광주과학기술원 정보통신공학과) ;
  • 김홍국 (광주과학기술원 정보통신공학과)
  • Published : 2004.04.01


In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25$\mu\textrm{m}$ technology indicates 17% lower latency than GasP.