2-5 Gb/s 클럭-데이터 복원기를 위한 위상 비교기 설계 연구

A Design Study of Phase Detectors for the 2.5 Gb/s Clock and Data Recovery Circuit

  • 이영미 (경북대학교 전자전기컴퓨터학부) ;
  • 우동식 (경북대학교 전자전기컴퓨터학부) ;
  • 유상대 (경북대학교 전자전기컴퓨터학부) ;
  • 김강욱 (경북대학교 전자전기컴퓨터학부)
  • 발행 : 2002.11.01

초록

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.