High-Level Test Generation for Asynchronous Circuits Using Signal Transition Graph

신호 전이그래프를 이용한 비동기회로의 상위수준 테스트 생성

  • 오은정 (광주과학기술원 정보통신공학과 병행시스템연구실) ;
  • 김수현 (광주과학기술원 정보통신공학과 병행시스템연구실) ;
  • 최호용 (충북대학교 전기전자공학부) ;
  • 이동익 (광주과학기술원 정보통신공학과 병행시스템연구실)
  • Published : 2000.06.01


In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.